AR# 32274: Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Release Notes and Known Issues for ISE 11.1
AR# 32274
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Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Release Notes and Known Issues for ISE 11.1
描述
This Release Notes and Known Issues Answer Record is for the Endpoint Block Plus Wrapper v1.10 and v1.10.1, released in ISE 11.1, and contains the following information:
- General Information - New Features - Bug Fixes - Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf
解决方案
General Information
The LogiCORE Endpoint Block Plus for PCI Express requires a license to generate and implement the core. There is no charge for this license.
- ISE 11.1 design tools support - Added support for SecureIP simulation models for VCS - Added support for Virtex-5 TX150T-FF1156
Resolved Issues
Fixed in v1.10
CR 490064 - Receipt of Back-to-Back ACKs causing TX Lockup - 8 lane only, when lane reversal in play. Issue resolved where receipt of Back-to-Back ACK DLLPs could cause the Integrated Hard Block to Lock-up in the transmit direction. This issue only affected the 8 lane product, when lane reversal is in play.
CR 479824 - Issue resolved with VHDL simulations for FXT/TXT Issue resolved where FXT/TXT x8 VHDL simulations were failing due to error in the script.
CR 472244 - TS2 link Upconfigure bit causing failure to link train Issue resolved where setting the Autonomous bit in a TS1 caused the Integrated Hard Block for PCI Express to fail to link train.
CR 478551- Incorrect data in PIO example design memory space due to byte swapping of write data - VHDL only. Issue resolved where the PIO example design memory space contains incorrect data due to byte swapping on data written into the memory. This is a VHDL only issue.
CR 491602 - Tx Sync module failing to register 1 on wait_stable_r causing SYNC_DONE to not assert. Issue resolved where if the resetdone asserted before clock_lock, txsync was not registering 1 for wait_stable_r when the user_clk is available.
CR 493462 - Added 100 microsecond delay on when the PLL lock asserts. Added a 100 microsecond delay on when the clock_lock (PLL Lock) asserts, based on Virtex-5 FPGA datasheet DC & Switching characteristics.
CR 493001- Added PAR priority placement attributes and removed LUT LOCs in UCFs. Added PAR priority placement attributes and removed LUT LOCs from UCFs
CR 499701- Removed SIM_MODE = LEGACY setting from GTX wrapper. Removed SIM_MODE = LEGACY setting from GTX wrapper, as the VHDL simulation issue has been resolved (CR 479824 above).
CR 492413 - Completions with 1DW data and TLP Digest being dropped when ECRC TRIM is enabled. Issue resolved where completions with 1 DW data payload and a TLP Digest were getting dropped in the receiver, when ECRC TRIM is enabled.
CR 502646 - Issue where delay added in CR 493462 did not account for differences caused between using 100 and 250 MHz clock during simulation. Adjusted counter so that delay is a 100 microsecond regardless of reference clock speed.
Fixed in v1.10.1
CR 504873 - Issue where trn_tdst_rdy_n deasserts stalling TX data path forever. Resolved issue causing the work around for the "TX Transmission Issues Due to Lack of Data Credits" listed in UG197 to incorrectly stall the transmission of TLPs forever.
CR 506462 - Issue where completion lost on RX path when using completion streaming. Resolved issue where delay in switching between different RX channel FIFOs on block was not efficient, causing an incoming completion to be lost.
CR 518037 - Issue where XCORE_INFO incorrectly reports ISE10.1.3 Resolved issue where XCORE_INFO incorrectly reports ISE10.1.3.
CR 436916- Per Vector Masking Bit incorrectly set inside MSI Control Register. Resolved issue where the Per Vector Masking Bit in the MSI control register was always enabled. This bit is disabled now, since per vector masking is not supported.
CR 493708 - Power management transition from D0 to D3hot to D0 can cause transmit stall. Resolved issue where a programmed power management transition from D0 to D3hot caused the transmit path to stall forever by deasserting trn_tdst_rdy_n
Known Issues There are three main components to the Endpoint Block Plus Wrapper for PCI Express:
- Virtex-5 FPGA Integrated Block for PCI Express - Virtex-5 FPGA GTP/GTX Transceivers - Block Plus Wrapper FPGA fabric logic
(Xilinx Answer 31210) Endpoint Block Plus Wrapper for PCI Express v1.10 and v1.10.1 - Interrupt Status bit not set when generating Legacy Interrupt.
(Xilinx Answer 31211) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Link transitioning to L0s causes BAR settings to reset.
(Xilinx Answer 31460) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - CORE Generator Customization GUI, Page 7 TXPREEMPHASIS wrong for FXT.
(Xilinx Answer 31646) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Dual Core UCF problems.
(Xilinx Answer 31647) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Dual core implement_dual.bat missing.
(Xilinx Answer 31704) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Importing a v1.8 XCO to v1.9 causes "Error:sim228 -An Invalid core configuration has been detected during Customization"
(Xilinx Answer 31850) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Simulation testbench writes to incorrect address for device control register.
(Xilinx Answer 32091) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Downstream port model drops completions with length 64 bytes and greater.
(Xilinx Answer 32727) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - MAP failing to complete due to predictable IP placement constraints
Revision History 09/22/2009 - Removed reference to UG493 and replaced with User Guide 05/20/2009 - Added 32727 04/27/2009 - Initial Release for 11.1