AR# 31843: Endpoint Block Plus Wrapper v1.9 for PCI Express - Power management transition from D0 to D3hot to D0 can cause transmit stall
AR# 31843
|
Endpoint Block Plus Wrapper v1.9 for PCI Express - Power management transition from D0 to D3hot to D0 can cause transmit stall
描述
Known Issue: v1.9, v1.8, v1.7.1, v1.6.1, v1.5.2
If the system issues a configuration write to the power management register to move the endpoint from D0 to D3hot and then back to D0, it might cause a lock up on the endpoint's transmit path. After the power management transitions, TLPs might no longer get transmitted to the block and might be stalled in the wrapper.
解决方案
This issue only affects a Block Plus core generated as a x1 interface using a 62.5 MHz user interface clock. The x4 and x8 cores and x1 core using 125 or 250 MHz interfaces are not affected by this issue.
This happens because transitioning from D3hot to D0 causes an internal soft reset to occur, which then resets logic needed to work around the Block Known Restriction "TX Transmission Issues Due to Lack of Data Credits". See UG197 for more information on this issue:
This logic monitors data credits read from the block and will transfer TLPs only if sufficient credits exist to avoid this problem. The power management transition from D3hot back to D0 resets this logic, causing subsequent packets to be stalled.
Normally, these power management transitions occur if the device driver is disabled and then re-enabled.
To work around this issue, a system reset can be asserted.
A fix for this is available in the v1.9 Rev 3 patch. See (Xilinx Answer 31572) for access to the patch.
Revision History
02/25/2009 - Added that patch available. 02/12/2009 - Added information about x1. 10/24/2008 - Initial Release