AR# 31458

描述

解决方案

GTX Answer Records:

(Xilinx Answer 30931) - Virtex-5 GTX RocketIO - MGTAVCC Power recommendations for unused tiles between calibration resistor and instantiated tiles
(Xilinx Answer 30953) - Virtex-5 GTX RocketIO - DFE clock delay calibration override
(Xilinx Answer 30958) - Virtex-5 GTX RocketIO SIS Kit - GTX REFCLK power supply labeled MGTAVCCPLL, should be MGTAVTTX
(Xilinx Answer 31316) - Virtex-5 GTX RocketIO Wizard - Generating >5Gb/s wrappers for -2CES9988 parts
(Xilinx Answer 31423) - Virtex-5 GTP/GTX RocketIO - SIM_MODE attribute description
(Xilinx Answer 31457) - Virtex-5 GTX RocketIO - SATA Spread Spectrum Clocking attribute changes
(Xilinx Answer 31509) - Virtex-5 GTX RocketIO - TXKERR and TXRUNDISP meaning for a 4-byte interface
(Xilinx Answer 31968) - Virtex-5 GTX RocketIO - Rate change implementation steps
(Xilinx Answer 31987) - Virtex-5 GTX/GTP RocketIO - Disparity Errors at near-end interface when using Far-end PCS Loopback
(Xilinx Answer 38410) -Virtex-5 FPGA GTP/GTX Transceiver: What is the RX impedance value before and after power up and configuration?
(Xilinx Answer 32164) - Virtex-5 GTX RocketIO - Data errors with CLK_COR_ADJ_LEN = 1 or 3 during asynchronous operation
(Xilinx Answer 33925) - Virtex-5 GTX RocketIO Wizard v1.6 - "Warning : At time 55134250, RDEN on AFIFO36_INTERNAL instance testbench.DUT.xaui_block.rocketio_wrapper_i.tile1_gtp0_cc_2b_1skp_i.cc_fifo.INT_FIFO.genbl"