AR# 30802: 10.1.01 System Generator for DSP - Release Notes/README and Known Issues List
AR# 30802
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10.1.01 System Generator for DSP - Release Notes/README and Known Issues List
描述
Keywords: MATLAB, Simulink, errata, KI, SysGen, 10.1.01
This Answer Record contains the Release Notes and Known Issues for System Generator for DSP 10.1.01.
解决方案
For System Generator for DSP release notes from other release versions, see (Xilinx Answer 29595).
Release Notes and Known Issues in System Generator for DSP 10.1.01
System Generator for DSP 10.1.01 is a minor update. Please read the documentation. It answers questions you might have about changes to the functionality or the look from previous versions of System Generator for DSP. The System Generator User Guide is accessible in PDF format at: http://www.xilinx.com/ise/optional_prod/system_generator.htm
Software Support Issues
- What software is required to install System Generator for DSP? See (Xilinx Answer 17966).
System Generator Enhancements Enhanced UCF Support for EDK Import Flow The handling of UCF (User Constraint File) files in the EDK import flow has been enhanced to support larger UCF file sizes. The UCF file of an imported XPS project is now parsed and modified to form a new UCF file based on the settings of the EDK Processor block. The user can view and modify the original UCF file and then reimport the XPS project. Enhanced PLB Dual Clock Support Xilinx Platform Studio projects that use clock generators to drive the PLB bus, MicroBlaze processor and other hardware peripherals with different clocks, can now automatically be imported into System Generator for HDL netlisting and hardware co-simulation.
Xilinx DSP Blockset Enhancements CIC Compiler 1.2 Update to existing block - Simulation speedup of ~4x as compared to CIC Compiler 1.1 DDS Compiler 2.1 Update to existing block - Core generation time has been reduced by ~10x, compared to previous versions of the DDS Compiler. - Ability to specify negative frequencies. - In the previous version of the DDS Compiler, after reset has been deasserted, the RDY output goes high 1-cycle too early; this error has been corrected.
Xilinx Block Set Issues
- Why does the DSP48 Opmode block have invalid characters reading "PCIN>>17" instead of "PCIN>>17"? See (Xilinx Answer 30790). - Why are there mismatches in my post-translate, post-MAP, or post-PAR simulation if I use the DCM for my "Multirate Implementation"? See (Xilinx Answer 30316). - Why does the post-MAP resource estimation return zero for all resources except IOBs? See (Xilinx Answer 30675).
General Issues
- When using System Generator on a 64-bit XP machine, why do I receive a message stating, "There is a problem with your Xilinx ISE installation or with your Xilinx environment variable" and "could not run java.exe"? See (Xilinx Answer 29512). - When trying to use System Generator on Windows Vista, why do I receive an error stating "gcc.exe: installation problem, cannot exec 'cc1': No such file or directory. Error occurred during Simulation Initialization"? See (Xilinx Answer 30977). - I cannot add my System Generator Project (.SGP) file to my ISE Project Navigator project. Why? See (Xilinx Answer 30676). - Simulation does not use the automatically generated Verilog testbench and stimulus files. See (Xilinx Answer 30308). - Why do I see an instantiated register called "xlpersistentdff" in a System Generator for DSP design? See (Xilinx Answer 24257). - JTAG Hardware Co-Sim with non-Xilinx parts in the chain causes error. See (Xilinx Answer 19599). - Why do I receive "Error 0001: caught standard exception" error when using IBM Clear Case? See (Xilinx Answer 24263). - Why do post-PAR simulation mismatches occur when running a design at faster than 200 MHz? See (Xilinx Answer 24268). - I cannot generate an NGC, Bitstream, Timing Analysis, or Hardware in the Loop target when using Synplify as my synthesis tool. Why? See (Xilinx Answer 24273). - Why are there simulation mismatches at the beginning of the HDL simulation generated from System Generator for DSP when Synplify is used for synthesis? See (Xilinx Answer 29170). - Why does the design fail to generate when using a FIFO block, From FIFO block, or To FIFO block in the design, and the target path is more than 160 characters? See (Xilinx Answer 23614). - When attempting to export a System Generator model as an FSL PCore for EDK, I receive "Error running xledkpostgen." See (Xilinx Answer 30959). - Why do I receive "ERROR:Simulator:798 - Unknown signal 1073807366 received" and "Warning:HDLCompiler:746 - "N:/K.31/rtf/vhdl/src/ieee/numeric_std.vhd" Range is empty" when simulating an IP core in System Generator 10.1? See (Xilinx Answer 31065). - Why do I receive the message "xledkpostgen>PLBPcoreBuilder at 234" when netlisting my EDK PCORE design from System Generator? See (Xilinx Answer 31068). - When I use asymmetrical reloadable coefficients in my FIR Compiler, the results are incorrect. See (Xilinx Answer 31069). - Why do I get the error "standard exception: XNetlistEngine: XTreeView::lookum_vertex: lookup failed" when I try to generate my design? See (Xilinx Answer 31071). - Why do I receive "Error in 'Design/block' while executing C MEX S-function 'sysgen', (mdlTerminate), at time 10. MATLAB error message: Unexpected unknown exception from MEX file" when I simulate my System Generator model? See (Xilinx Answer 31095). - Why do I receive the message "Failed to execute command "project set {Synthesis Tool} {Synplify Pro (VHDL/Verilog)}"" when trying to use Synplify Pro for my synthesis tool form System Generator? See (Xilinx Answer 31112).