AR# 22653

描述

This Answer Record contains the Release Notes and Known Issues for System Generator for DSP 8.1.

解决方案

For System Generator for DSP release notes from other release versions, see (Xilinx Answer 29595).

Known Issues in System Generator for DSP 8.1

System Generator for DSP 8.1 is a major update. Please read the documentation, as it provides answers to questions that you might have about changes to the functionality or the look from previous versions of System Generator for DSP. The System Generator User Guide PDF Version is accessible from:

http://www.xilinx.com/products/design_resources/dsp_central/grouping/index.htm

Support Software Issues

1. What software do I need to install System Generator for DSP? See (Xilinx Answer 17966).

2. XST bus elaboration might cause interface changes. See (Xilinx Answer 18650).

3. Why is my old System Generator for DSP missing, or has disappeared when running xlVersion after installing 8.1? See (Xilinx Answer 22756).

Xilinx Blockset Issues

1. Why do I get an algebraic feedback loop error when using the Reed Solomon Encoder or Decoder in a feedback loop? See (Xilinx Answer 22714).

2. Why do I see simulation mismatches with the DDS v4.0 when both the reset port and pipelining are enabled? See (Xilinx Answer 22709).

3. PicoBlaze compiler script fails when using long module names. See (Xilinx Answer 16924).

4. When I use the xlUpdateModel script, why does the VOUT pin not work correctly for the Reed Solomon Encoder if the BYPASS option is selected? See (Xilinx Answer 22712).

5. Why does XST "Error 1370 ..." occur when using Verilog as my target language with a DDS v4.0 or v5.0 in my design? See (Xilinx Answer 22713).

6. Simulation mismatched for the reloadable DA FIR when performing back-annotated simulation. See (Xilinx Answer 19505).

7. Why does my System Generator for DSP 6.3 or 7.1 design (which passed generics to the black box for port widths) fail in System Generator for DSP 8.1? See Xilinx (Answer 22715).

8. Reset must be asserted when using the embedded option for the FIFO block. See (Xilinx Answer 20201).

9. Verilog simulation mismatched when using the FIFO block. See (Xilinx Answer 20205).

General Issues

1. The following error is reported during generation: "Undefined function or variable." See (Xilinx Answer 15190).

2. Generation fails when the Simulation Stop Function is defined for a model. See (Xilinx Answer 18623).

3. User Hardware Co-Sim files disappear when installing System Generator for DSP update. See (Xilinx Answer 18646).

4. JTAG Hardware Co-Sim with non-Xilinx parts in the chain causes error. See (Xilinx Answer 19599).