General Description: This README Answer Record contains the Release Notes for 7.1i Service Packs.
The Release Notes include installation instructions and a list of the issues that have been fixed. Note that ISE Service Packs are cumulative; therefore, fixes found in Service Pack 1 are also found in Service Packs 2.
Note: EDK 7.1i SP2 REQUIRES ISE 7.1i SP3
解决方案
1
A successful installation of Xilinx EDK 7.1i Service Pack "x" updates your software version number to 7.1.0xi.
NOTES: 1. The destination directory specified during the set-up operation must contain an existing Xilinx EDK installation. Only existing files are updated. 2. You must set the XILINX and XILINX_EDK environment variables before installing the Service Pack.
Installation Instructions for Red Hat Linux & Solaris Users 1. Download "EDK_7_1_0xi_<platform>.zip from: http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp 2. Move the zip file to an empty "staging" area, and unzip the downloaded file.
For example: mv EDK_7_1_0xi_<platform>.zip /home/<staging_dir> cd /home/<staging_dir> unzip EDK_7_1_0xi_<platform>.zip
3. Run "setup"
2
Issues Fixed by 7.1i Service Packs
PlatGen (SP1) 6.3 EDK - PlatGen - Verilog `include compile directive in pcore not supported (Xilinx Answer 21334)
(SP2) 7.1i EDK - An EDK design with a floating point unit (FPU) fails in Virtex, Virtex-E, Spartan-II and Spartan-IIE (Xilinx Answer 21677)
Processor IP (SP2) 7.1i EDK SP2 - plb_ddr 1.10a hard to meet timing in Virtex-4 (Xilinx Answer 21700)
(SP2) 7.1i EDK SP2 - DCR devices might errantly acknowledge requests when PPC has C_DCR_RESYNC=1 option (Xilinx Answer 21701)
(SP2) 7.1 EDK - plb_ipif_v2_01_a Slave attachment does not respond to IP master read when C_Burst_Enable is False (Xilinx Answer 21485)
(SP2) 7.1i EDK SP2 - PLB DDR2 might fail in timing simulation when using ASYNC FIFO 4.0 (Xilinx Answer 21706)
(SP2) 7.1i EDK SP2 - OPB GPIO V3_01_B may cause timing difficulties in a MicroBlaze or PowerPC system (Xilinx Answer 21705)
(SP2) 7.1 EDK - Processor IP Core, the XST tool in 7.1 EDK and higher is using one additional BUFG than 6.3 EDK for OPB SPI and other cores (Xilinx Answer 21569)