I2S-TDM: I2S/TDM Multichannel Audio Transceiver

  • 产品编号: I2S-TDM
  • 供应商: CAST, Inc.
  • Certified Partner

产品描述

The I2S-TDM IP core is a highly configurable, full-duplex, multichannel serial audio transceiver. The transceiver can act as a controller (master) or a target (slave) for Inter-IC Sound (I2S) and Time-Division Multiplexed (TDM) audio interfaces, exchanging mul-ti-channel audio samples over a configurable number of serial lines (pins). The I2S-TDM offers a number of configuration options to satisfy a wide range of serial audio interface requirements. The operation mode (controller or target), sample width, sample rate, frame format, number of channels and their allocation to physical lines are all programmable at run time. At synthesis time, designers can choose the maximum number of audio channels and serial data lines the transceiver can support. The core is designed for ease of use and integration and adheres to the industry’s best coding and verification practices. The core’s control and status registers (CSR) are accessed through a 32-bit AMBA® APB interface, or, optionally, an AXI4 Lite inter-face. The host system exchanges audio data with the core either via this CSR interface or via dedicated AXI4-Stream interfaces. The system interfaces operate with a clock that is independent from the audio master and serial bit clocks, and the core implements clean clock domain crossing boundaries.


主要特性与优势

  • Maskable interrupts based on run-time programmable FIFO occupancy thresholds
  • I2S/TDM (master) or target (slave)
  • Audio data input/output via 32-bit AMBA APB or AXI4 Lite CSR interface, or via dedicated 32-bit AXI-Stream interfaces
  • Run-time programable sample width (2 to 32 bits), sample rate (bit clock period and polarity), and frame format (Fsync/WS duration, delay and polarity)
  • Synthesis-time configurable number of receive and transmit data lines (pins), and maximum number of audio channels
  • Full-duplex operation
  • Supports left-justified and right-justified I2S and TDM audio data formats

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Spartan-7 Family XC7S50 -1 Vivado 2020.2 390 945 2 0 0 0 250
ARTIX-7 Family XC7A35T -1 Vivado 2020.2 404 975 2 0 0 0 250
KINTEX-U Family XCKU040 -1 Vivado 2020.2 0 975 2 0 0 0 400

IP 质量指标

综合信息

数据创建日期 Apr 05, 2023
当前 IP 修订号 1.21
当前修订日期已发布 Jan 27, 2023
第一版发布日期 Jan 15, 2023

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 2
可否提供参考? N

交付内容

可供购买的 IP 格式 Source Code, Netlist
源代码格式 Verilog
是否包含高级模型? N
提供集成测试台 Y
集成测试台格式 Verilog
是否提供代码覆盖率报告? Y
是否提供功能覆盖率报告? Y
是否提供 UCF? XDC
商业评估板是否可用? N
评估板所用的 FPGA N/A
是否提供软件驱动程序? Y
驱动程序的操作系统支持 N/A

实现方案

代码是否针对 Xilinx 进行优化? N
定制 FPGA 优化技术 None
所支持的综合软件工具及版本 Synplicity Synplify; Mentor Precision; Vivado Synthesis
是否执行静态时序分析? Y
AXI 接口 AXI4-Stream, AXI4-Lite
是否包含 IP-XACT 元数据? Y

验证

是否有可用的文档验证计划? Yes, document only plan
测试方法 Directed Testing
断言 N
收集的覆盖指标 Code, Functional
是否执行时序验证? N
可用的时序验证报告 N
所支持的仿真器 Cadence NC-Sim; Cadence IUS; Mentor ModelSIM; Mentor Questa; Synopsys VCS

硬件验证

在 FPGA 上进行验证 N
已通过的行业标准合规测试 N
是否提供测试结果? N