DSP48 Block

The most complex computational block available in a Xilinx FPGA is the DSP48 block shown below.

Figure: Structure of a DSP48 Block

The DSP48 block is an arithmetic logic unit (ALU) embedded into the fabric of the FPGA and is composed of a chain of three different blocks. The computational chain in the DSP48 contains an add/subtract unit connected to a multiplier connected to a final add/subtract/accumulate engine. This chain allows a single DSP48 unit to implement functions of the form:

P=Bx(A+D)+C

Or

P +=Bx(A+D)

The DSP48 block can be used by SDAccel™ to perform a lot of the computational load within OpenCL kernels. The synthesis flow inside the SDAccel tool targets this block automatically.