Improving Kernel Frequency

One of the key advantages of an FPGA is its flexibility and capacity to create customized design specifically for your algorithm to improve throughput and save power. The downside of creating custom logic is that the design will need to go through traditional FPGA design flow and meet the target frequency each time the design is built. The guidelines below will generally help you improve achievable kernel frequency:

• Partition design into sub-functions with reasonable size for each function.
• Pipeline each sub-function to get best initiation interval (II).
• Create top function with sub-function calls only.
• Optimize the top function with DATAFLOW attribute/pragma.
• Keep loop body small in each sub-function.
• Watch out for warnings on high fanout net in the kernel and recode the design accordingly.
• Use pipeline and array partition attributes/pragma precisely to have a good balance of performance and design size.