Exploring Kernel Optimizations Using Vivado HLS

All kernel optimizations, using OpenCL™ or C/C++, can be performed from within the SDAccel™ Environment. The primary performance optimizations, such as those discussed in this chapter (pipelining function and loops, applying dataflow to enable greater concurrency between functions and loops, unrolling loops, etc.), are performed by the Xilinx® FPGA design tool Vivado® HLS.

Vivado HLS is called automatically by the SDAccel Environment, however you also have the option of launching Vivado HLS directly from within the SDAccel Environment. Using Vivado HLS in standalone mode enables the following enhancements to the optimization methodology:

Focusing solely on the kernel optimization, there is no requirement to execute emulation.
The ability to create multiple solutions, compare their results, and explore the solution space to find the most optimum design.
Note: The Vivado HLS INTERFACE directive used to specify the kernel interface protocol is ignored in the SDAccel Environment.
The ability to use the interactive Analysis Perspective to analyze the design performance.

IMPORTANT!: Only the kernel source code is incorporated back into the SDAccel Environment. After exploring the optimization space, ensure that all optimizations are applied to the kernel source code as OpenCL attributes or C/C++ pragmas.

To open Vivado HLS in standalone mode, from the Project Setting pane, select the Vivado HLS icon (shown in the top right-hand of the following figure).