pragma SDS data sys_port

Description

This pragma must be specified immediately preceding a function declaration, or immediately preceding another #pragma SDS bound to the function declaration, and applies to all the callers of the function.

This pragma overrides the SDSoC compiler default choice of memory port. If the sys_port pragma is not specified for an array argument, the interface to the external memory is automatically determined by the SDSoC system compilers (sdscc/sds++) based on array memory attributes (cacheable or non-cacheable), array size, data mover used, etc.

Syntax

The syntax for this pragma is: 
#pragma SDS data sys_port(ArrayName:port)
Where:
  • ArrayName: Specifies one of the formal parameters of the function to assign the pragma to.
  • port: Must be ACP, AFI, or HPC.
    • The Zynq®-7000 SoC provides a cache coherent interface (S_AXI_ACP) between programmable logic and external memory, and high-performance ports (S_AXI_HP) for non-cache coherent access (AFI).
    • The Zynq UltraScale+ MPSoC provides a cache coherent interface (S_AXI_HPCn_FPD), and non-cache coherent interface called (S_AXI_HPn_FPD).
  • Multiple arrays can be specified in one pragma, separated by commas:
    #pragma SDS data sys_port(ArrayName1:port, ArrayName2:port)

Example 1

The following code snippet shows an example of using this pragma:
#pragma SDS data sys_port(A:AFI)
void foo(int A[1024], int B[1024])

In the above example, if the caller passes an array allocated with cacheable allocation calls such as malloc or sds_alloc to the A argument, the SDSoC compiler uses the AFI platform interface, even though this might not be the optimal choice.

See Also

  • SDSoC Environment Optimization Guide (UG1235)
  • SDSoC Environment User Guide (UG1027)