SDAccel Migration Summary

The following table specifies changes to existing flows and scripts which are required when using the 2017.4 release.

Table 1. SDAccel Migration Summary
Area	2017.4 Behavior	Required Update for 2017.4
DSA	5.x DSA are the primary supported DSA for 2017.4. You can use existing 4.X DSA from previous release, with the 2017.2 xocc options	Xilinx strongly recommends that you update to 5.x DSA Platforms, specify the platform using the -platform option.
DSA	Now use "_" character as separator instead of ":".	Platform names now use the character “_” as a separator. This requires updating the DSA name in the xocc command option --platform.
xocc options	Single step compilation no longer supported. Use makefile flow.	Kernels must be compiled using –compile (-c) option and then linked using the -link (-l) option as two separate xocc commands. When using the SDx™ GUI, it automatically generates the correct makefile with this style of xocc switches.
	If using multiple DDR banks, the --xp map_connect option has been removed and replaced with the -sp options with a much simpler syntax.	The new xocc command option –sp is now used to specify system ports. The following shows how an existing map_connect option may be changed for 2017.4. (2017.2) `--xp misc:map_connect=add.kernel.krnl_idct_1.M_AXI_GMEM.core.OCL_REGION_0.M00_AXI` (2017.4) `--sp krnl_idct_1.m_axi_gmem:bank0`
	The location of include files has changed.	If using Xilinx include files, change the include pathname from `-I$(XILINX_SDACCEL)/Vivado_HLS/include/` to `-I$(XILINX_SDACCEL)/include`
Host Code	Compiling host code on an Ubuntu OS.	When compiling host code on an Ubuntu OS, you must explicitly use –std=c++14. Note that system header file, sys/cdefs.h is located in the directory /usr/include/x86_64-linux-gnu and not in the /usr/include directory. This may require an update to your `include` paths.
	If using more than one xclbin file, the first must be released before second is loaded.	For multiple xclbin files you must now free the current xclbin using clReleaseProgram() and clReleaseKernel() before proceeding to load subsequent xclbin files.
	Multiple kernels accessing the same DDR.	If there are independent kernels that access the same DDR, and there is a cyclic dependency between them, it may lead to a deadlock. You need to break the dependency between the kernels, either by accessing different DDRs for access, or by ensuring that there is synchronization between them. For example, if there are two kernels, each accessing the DDR bank, for a total of 4 read and write operations (two reads and two writes each), you should use one DDR for the reads for the two kernels and one DDR for doing the writes for the same kernel.
	Accessing memory size beyond what was linked in xocc might have worked.	Host code will only have access to memory size that is available to kernel and will be dependent on no banks being used in design. Previous designs that accessed memory size beyond allocated will not work as xocc will optimize away DDR interfaces that are not being set using –p.
	Shared library	When you use HLS math library in SDx host code, you must add additional linkage information to your Makefile to find the dynamic library. For example: `$(XILINX_VIVADO)/lnx64/lib/csim -lhlsmc++-GCC46`
C/C++ OpenCL Kernel Code	Pipes must now use all lower case names.	The variable used in pipes must now all be lower cases. For example, the following cannot use ‘pipe int inFifo’, and must use all lower case. `pipe int infifo _attribute_((xcl_reqd_pipe_depth(16)));`
	The OpenCL 2.0 image functions were supported by default. These now require a compiler option.	Use of OpenCL 2.0 image functions generates an error, and require you to enable 3.1 compiler using the xocc command option `--xp param:compiler.version=31`.
	Enhance memory coalescing to improve memory bandwidth and speed up kernel execution	Loop vectorization may automatically happen to improve memory bandwidth. Sometimes this will increase resource usage. You can turn this off by using the following at the loop impacted. `#pragma nounroll`
	The xcl_dependence attribute requires using the 3.1 compiler version.	Use of the xcl_depedence attribute generates an error. You will have to either remove the attribute or enable 3.1 compiler using the xocc command option--xp param:compiler.version=31.
	Default data width of OpenCL Kernel interface.	The default data width of the OpenCL Kernel AXIM interface has changed to 512 bits. This should improve the performance of kernels but may impact timing closure on some designs.
	C and C++ kernels which use the interface bundle option.	The bundle option, as shown below for AXI and AXI4-Lite interface must use all lower case names for the bundle name. In both cases below, the name “bar” is all lower case. `#pragma interface s_axilite port=foo bundle=bar #pragma interface m_axi port=foo bundle=bar`
RTL Kernel	RTL Kernel XO file Packaged Using RTL Kernel Wizard	Rerun the RTL Kernel Wizard and choose same options as from 2017.4_sdx. In the Vivado Project, re-introduce your RTL adapting to top level AXI interface port list. Then repackage the kernel to generate a new XO file. This will ensure the RTL kernel has all the latest meta data required for 2017.4 tool-flow and runtime.
	RTL Kernel Packaged by user without using RTL Kernel Wizard	RTL kernels manually packaged, must be re-packaged to work with 2017.4. The following commands added to inject required new meta data: `set_property sdx_kernel true [ipx::current_core] set_property sdx_kernel_type rtl [ipx::current_core]`
		Every IP must have primary clock named `ap_clk` which drives the IP and all AXI interfaces on the IP. It can optionally have a secondary clock, but this must be named `ap_clk_2`. The former has associated reset port `ap_rst_n` and when the latter exists, it must have a corresponding reset port `ap_rst_n_2`.
		If you are manually packaging RTL Kernel (not using RTL Kernel Wizard), port interface names has to be consistent between kernel.xml and component.xml (case sensitive).
	RTL kernel with pipes	Within the kernel.xml, stream pipes names must be all lower case. No mixed or upper case will be supported. Global BRAM pipe connections are not supported.
	Hand edited RTL kernel.xml	Every declared port (port/@name) must be mapped from, i.e., equal to some kernel argument (arg/@port).
Profiling	Profiling hardware may be dynamically added to any DSA and is no longer required to be pre-built in the platform. This requires an update to the xocc command options.	Profiling is now performed as two-step process of enabling the collection of profiling data and the saving the data. Enable profile instrumentation by compiling the kernels with the `–profile_kernel` option. Set `profile=true` in the sdaccel.ini file to collect profile data.
	Use `sdx_analyze profile <options>`. to generate profile summary report	`sda2wdb` used to generate application timeline trace report is replaced by`sdx_analyze`.
	Use `sdx_analyze trace <options>` to generate application timeline trace report.	`sda2wdb` used to generate application timeline trace report is replaced by `sdx_analyze`
	`sdxsyschk` utility not available to check Xilinx PCIe platform status.	Deprecated and replaced by xbsak scan command.
	Profiling HTML reports are not automatically generated.	Run `sdx_analyze profile --input sdaccel_profile_summary.csv --format html` to generate the html profile summary.