SDAccel Development Environment Changes for 2017.4

The following are changes to existing features in the SDAccel™ development environment in this release:

  • DSAs
    • New 5.x version DSAs ("dynamic" DSAs), which are now configurable at link time to free up resources for kernels, reduce hardware compile times, and improve timing closure in Vivado.
    • In dynamic platforms, logic in the DSA, which is not required, such as the logic used to implement an unused DDR memory is optimized away during compilation.
    • When using 4.x or earlier DSAs, Software and Hardware Emulation require the prepending of the 4.x DSA libraries to the LD_LIBRARY_PATH.

    • When using 4.x or earlier DSAs, only design examples from the 2017.2 or earlier Xilinx Github may be used.

      Note: All 2017.4 SDAccel Github examples will only work with 5.x DSA versions.

  • xocc compiler

    • xocc compiler for OpenCL kernel compilation has been upgraded to LLVM 3.9.

    • Starting 2017.4, two advanced transformations were added that should help getting consistently high global memory bandwidth utilization in OpenCL kernels. This is achieved in two complementary ways:

      • Widening / Vectorization of the datapath of the memory interface.

      • Enhanced burst inference on the array access to the memory interface.

      When these two transformations are triggered, speed-ups by as much as 5X can be achieved (usually, up to saturation of the memory bandwidth).

  • Xilinx SDAccel Runtime
    • Use of multiple xclbin files.
      • Cases where the host code uses multiple Xclbin files must now free the current xclbin using clReleaseProgram() and clReleaseKernel() before proceeding to load subsequent xclbin files.
    • Updated memory selection.
      • When using multiple DDR memories, the selection is now made at compile time using the xocc command line switch –sp and the map_connect option is now deprecated.
      • Existing host code, which specifies DDR banks using clCreateBuffer, should be updated to use the new command line switches.
    • Shared library
      • When you use HLS math library in SDx host code, you must add additional linkage information to your Makefile to find the dynamic library. For example:
        $(XILINX_VIVADO)/lnx64/lib/csim -lhlsmc++-GCC46
    • Enhanced xbsak features
      • The command line option dmatest now performs a DMA test on all the DDR banks used in the application and is specified in the xocc command line.
      • The command line option boot now forces a re-enumeration of the PCIe® bus and bus re-scanning.
      • The command line option scan is enhanced to provide more details about the OS.
      • The command line option query is enhanced to provide more details on each CU, such as the name, the kernel type, index, address and status.
  • Profile Features
    • Kernel Instrumentation is now controlled with the xocc compile option –profile_kernel
      • The compile time option allow the insertion of additional hardware logic to enable the generation of profiling data. This is enabled by default when using the IDE and may be disabled.
    • The Profile Summary Report and Timeline Trace Report are now generated using the sdx_analyze utility. This replaces the existing sda2protobuf and sda2wdb utilities.
  • Debug Features
    • A new xgdb utility is provided for Application Debug. This is required to peform Debug when using the command line interface.
      • This ensures any existing GDB debug features are not changed by SDAccel.
      • Application debug in the SDx GUI remains unchanged.
  • RTL Kernels
    • Ensure that all AXI outputs of RTL kernels are driven. Driverless outputs on RTL kernels may lead to xocc failures after synthesis step with messages like the following one. 
      Designs upgraded from V4.x DSAs to V5.x DSAs may be more sensitive to driverless output errors.