HLS Pragmas

Optimizations in Vitis HLS

In the Vitis software platform, a kernel defined in the C/C++ language, or OpenCL™ C, must be compiled into the register transfer level (RTL) that can be implemented into the programmable logic of a Xilinx device. The v++ compiler calls the Vitis High-Level Synthesis (HLS) tool to synthesize the RTL code from the kernel source code.

The HLS tool is intended to work with the Vitis IDE project without interaction. However, the HLS tool also provides pragmas that can be used to optimize the design, reduce latency, improve throughput performance, and reduce area and device resource usage of the resulting RTL code. These pragmas can be added directly to the source code for the kernel.

The HLS pragmas include the optimization types specified in the following table.

For detailed pragma information, refer to the Vitis HLS Flow.

Table 1. Vitis HLS Pragmas by Type
Type	Attributes
Kernel Optimization	pragma HLS aggregate pragma HLS bind_op pragma HLS bind_storage pragma HLS expression_balance pragma HLS latency pragma HLS reset pragma HLS top
Function Inlining	pragma HLS inline
Interface Synthesis	pragma HLS interface
Task-level Pipeline	pragma HLS dataflow pragma HLS shared pragma HLS stream
Pipeline	pragma HLS pipeline pragma HLS occurence
Loop Unrolling	pragma HLS unroll pragma HLS dependence
Loop Optimization	pragma HLS loop_flatten pragma HLS loop_merge pragma HLS loop_tripcount
Array Optimization	pragma HLS array_partition pragma HLS array_reshape
Structure Packing	pragma HLS aggregate pragma HLS dataflow