platforminfo Utility

Platform information and high-level description are reported.

Platform:      xdma
File:          /opt/xilinx/platforms/xilinx_u200_xdma_201830_1/
			   xilinx_u200_xdma_201830_1.xpfm
Description:   This platform targets the Alveo U200 Data Center Accelerator 
			   Card. This high-performance acceleration platform features 
			   up to four channels of DDR4-2400 SDRAM which are 
			   instantiated as required by the user kernels for high fabric 
			   resource availability, and Xilinx DMA Subsystem for PCI 
			   Express with PCIe Gen3 x16 connectivity.
Platform Type: Vitis

General information on the hardware platform is reported. For the Software Emulation and Hardware Emulation field, a "1" indicates this platform is suitable for these configurations. The Maximum Number of Compute Units field gives the maximum number of compute units allowable in this platform.

Vendor:                           xilinx
Board:                            U200 (xdma)
Name:                             xdma
Version:                          201830.1
Generated Version:                2018.3
Software Emulation:               1
Hardware Emulation:               1
FPGA Family:                      virtexuplus
FPGA Device:                      xcu200
Board Vendor:                     xilinx.com
Board Name:                       xilinx.com:au200:1.0
Board Part:                       xcu200-fsgd2104-2-e
Maximum Number of Compute Units:  60

The following shows the reported PCIe interface information.

  Interface Name: PCIe
  Interface Type: gen3x16
  PCIe Vendor Id:    0x10EE
  PCIe Device Id:    0x5000
  PCIe Subsystem Id: 0x000E

Reports the maximum kernel clock frequencies available. The Clock Index is the reference used in the --kernel_frequency v++ directive when overriding the default value.

  Default Clock Index: 0
  Clock Index:         1
    Frequency:         500.000000
  Clock Index:         0
    Frequency:         300.000000

Reports the valid SLRs in the platform.

  SLR0, SLR1, SLR2

The total available resources and resources available per SLR are reported. This information can be used to assess applicability of the platform for the design and help guide allocation of compute unit to available SLRs.

  Total...
    LUTs:  1051996
    FFs:   2197301
    BRAMs: 1896
    DSPs:  6833
  Per SLR...
    SLR0:
      LUTs:  354825
      FFs:   723370
      BRAMs: 638
      DSPs:  2265
    SLR1:
      LUTs:  159108
      FFs:   329166
      BRAMs: 326
      DSPs:  1317
    SLR2:
      LUTs:  354966
      FFs:   723413
      BRAMs: 638
      DSPs:  2265

  Type: ddr4
  Bus SP Tag: DDR
    Segment Index: 0
      Consumption: automatic
      SP Tag:      bank0
      SLR:         SLR0
      Max Masters: 15
    Segment Index: 1
      Consumption: default
      SP Tag:      bank1
      SLR:         SLR1
      Max Masters: 15
    Segment Index: 2
      Consumption: automatic
      SP Tag:      bank2
      SLR:         SLR1
      Max Masters: 15
    Segment Index: 3
      Consumption: automatic
      SP Tag:      bank3
      SLR:         SLR2
      Max Masters: 15
  Bus SP Tag: PLRAM
    Segment Index: 0
      Consumption: explicit
      SLR:         SLR0
      Max Masters: 15
    Segment Index: 1
      Consumption: explicit
      SLR:         SLR1
      Max Masters: 15
    Segment Index: 2
      Consumption: explicit
      SLR:         SLR2
      Max Masters: 15

The Bus SP Tag heading can be DDR or PLRAM and gives associated information below.

The Segment Index field is used in association with the SP Tag to generate the associated memory resource index as shown below.

Bus SP Tag[Segment Index]

For example, if Segment Index is 0, then the associated DDR resource index would be DDR[0].

This memory index is used when specifying memory resources in the v++ command as shown below:

v++ … --connectivity.sp vadd.m_axi_gmem:DDR[3]

There can be more than one Segment Index associated with an SLR. For instance, in the output above, SLR1 has both Segment Index 1 and 2.

The Consumption field indicates how a memory resource is used when building the design:

default

If the --connectivity.sp directive is not specified, it uses this memory resource by default during v++ build. For example in the report below, DDR with Segment Index 1 is used by default.

automatic

When the maximum number of memory interfaces have been used under Consumption: default have been fully applied, then the interfaces under automatic is used. The maximum number of interfaces per memory resource are given in the Max Masters field.

explicit

For PLRAM, consumption is set to explicit which indicates this memory resource is only used when explicitly indicated through the v++ command line.

The feature ROM information provides build related information on ROM platform and can be requested by Xilinx Support when debugging system issues.

  ROM Major Version:       10
  ROM Minor Version:       1
  ROM Vivado Build ID:     2388429
  ROM DDR Channel Count:   5
  ROM DDR Channel Size:    16
  ROM Feature Bit Map:     655885
  ROM UUID:                00194bb3-707b-49c4-911e-a66899000b6b
  ROM CDMA Base Address 0: 620756992
  ROM CDMA Base Address 1: 0
  ROM CDMA Base Address 2: 0
  ROM CDMA Base Address 3: 0

Although software platform information is reported, it is only useful for users that have an OS running on the device, and not applicable to users that use a host machine.

Number of Runtimes:            1
Linux root file system path:   tbd
Default System Configuration:  config0_0
System Configurations:
  System Config Name:                      config0_0
  System Config Description:               config0_0 Linux OS on x86_0
  System Config Default Processor Group:   x86_0
  System Config Default Boot Image:        
  System Config Is QEMU Supported:         0
  System Config Processor Groups:
    Processor Group Name:      x86_0
    Processor Group CPU Type:  x86
    Processor Group OS Name:   Linux OS
  System Config Boot Images:
Supported Runtimes:
  Runtime: OpenCL