Programming Model
The Vitis™ core development kit supports heterogeneous computing using the industry standard OpenCL™ framework (https://www.khronos.org/opencl/). The host program executes on the processor (x86 or Arm®) and offloads compute intensive tasks through Xilinx Runtime (XRT) to execute on a hardware kernel running on programmable logic (PL) using the OpenCL programming paradigm.
Device Topology
In the Vitis core development kit, targeted devices can include Xilinx® MPSoCs or UltraScale+™ FPGAs connected to a processor, such as an x86 host through a PCIe bus, or an Arm processor through an AXI4 interface. The FPGA contains a programmable region that implements and executes hardware kernels.
The FPGA platform contains one or more global memory banks. The data transfer from the host machine to kernels and from kernels to the host happens through these global memory banks. The kernels running in the FPGA can have one or more memory interfaces. The connection from the global memory banks to those memory interfaces are configurable, as their features are determined by the kernel compilation options.
Multiple kernels can be implemented in the PL of the Xilinx device, allowing for significant application acceleration. A single kernel can also be instantiated multiple times. The number of instances of a kernel is programmable, and determined by linking options specified when building the FPGA binary. For more information on specifying these options, refer to Linking the Kernels.
Kernel Properties
In the Vitis application acceleration development flow, kernels are the processing elements executing in the PL region of the Xilinx device. The Vitis software platform supports kernels written in C/C++, RTL, or OpenCL C. Regardless of source language, all kernels have the same properties and must adhere to same set of requirements. This is what allows the system compiler linker and Xilinx Runtime (XRT) to seamlessly interact with the kernels.
This topic describes the properties and requirements of kernels in the Vitis application acceleration flow. The following topics discuss how these requirements are satisfied based on the specific source languages:
Kernel Execution Modes
There are three types of kernel execution modes, as described in the following table. These modes are mutually exclusive; each kernel can only operate in one of these modes. Kernels with different execution modes can be linked together by the Vitis linker to form the FPGA binary.
Sequential Mode | Pipelined Mode | Free-Running Mode |
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Kernel Interfaces
Kernel interfaces are used to exchange data with the host application, other kernels, or device I/Os. There are three types of interfaces allowed, each designed for a particular kind of data transfer. It is common for kernels to have multiple interfaces of different types.
Functional Properties
The following table describes the functional properties of kernel interfaces.
Register | Memory Mapped | Streaming |
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Implementation Requirements
Each interface type must be implemented using specific hardware protocols. This is what allows the system compiler linker to integrate and compose kernels together with the platform. The following table describes the requirements for mapping interfaces to hardware.
Register | Memory Mapped | Streaming |
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Clock and Reset Requirements
C/C++/OpenCL C Kernel | RTL Kernel |
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C kernel does not require any input from user on clock ports and reset ports. The HLS tool will always generate RTL with clock port ap_clk and reset port ap_rst_n. |
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