Documents marked (DSL) are available at the Xilinx Design Security Lounge. Contact your Xilinx FAE or sign up for access.

User Guides	Design Files	Date
UG1508 - Versal Security Manual (DSL)
UG1540 - Versal Security Libraries User Guide (DSL)
Application Notes	Design Files	Date
XAPP1367 - Boot eFUSE-Enabled Fault Mitigation Features	Design Files
XAPP1359 - Versal ACAP External Secure Storage Using the PUF (DSL)	Design Files
XAPP1357 - Versal Asymmetric Hardware Root of Trust (A-HWRoT) Secure Boot (DSL)	Design Files
XAPP1358 - Versal Symmetric Hardware Root of Trust (S-HWRoT) Secure Boot (DSL)	Design Files
XAPP1369 - Versal ACAP Authenticated JTAG (DSL)	Design Files
Key Concepts	Design Files	Date
AM011 - Versal ACAP Technical Reference Manual - Platform Management Controller		10/27/2021
AM011 - Versal ACAP Technical Reference Manual - Platform Boot, Control, and Status		10/27/2021
AM011 - Versal ACAP Technical Reference Manual - Secure Boot Flow		10/27/2021
AM011 - Versal ACAP Technical Reference Manual - Platform Management		10/27/2021
AM011 - Versal ACAP Technical Reference Manual - Security Management		10/27/2021
AM011 - Versal ACAP Technical Reference Manual - Embedded Processor, Configuration, and Security Units		10/27/2021
AM011 - Versal ACAP Technical Reference Manual - Memory Protection		10/27/2021
AM011 - Versal ACAP Technical Reference Manual - Xilinx Memory Protection Unit		10/27/2021
AM011 - Versal ACAP Technical Reference Manual - Xilinx Peripheral Protection Unit		10/27/2021
AM011 - Versal ACAP Technical Reference Manual - System Memory Management Unit		10/27/2021
AM011 - Versal ACAP Technical Reference Manual - Test and Debug		10/27/2021
UG1304 - Versal ACAP Software System Developer Guide - Platform Loader and Manager		10/27/2021
UG1304 - Versal ACAP Software System Developer Guide - Boot and Configuration		10/27/2021
UG1304 - Versal ACAP Software System Developer Guide - Security		10/27/2021
UG1283 - Bootgen User Guide - Boot Time Security		10/22/2021
AM018 - Versal ACAP Register Reference Guide (DSL)
Design Advisories	Design Files	Date
AR76181 - Design Advisory Master Answer Record for Versal ACAP Devices
AR76449 - Design Advisory for Versal ACAP: Vcc_pmc must be connected to 0.7VDC if PUF is used
AR76171 - Design Advisory: Xilinx recommends that the user generates their own keys for fielded systems and then provide those keys to the development tools		04/23/2021