The Virtex®-7 FPGA VC7203 Characterization Kit provides the hardware environment for characterizing and evaluating 28 GTX (12.5Gbps) transceivers of the on-board Virtex-7 V485T FPGA. The VC7203 allows evaluation of the Integrated Bit Error Ratio Test (IBERT) demonstration using either the Vivado™ or ISE® design suites. Each GTX Quad and its associated reference clock are routed from the FPGA to a connector pad which is designed to interface with a Samtec BullsEye connector. A cable enabled with a BullsEye connector and 10 standard SMAs allows users to connect to a broad range of evaluation platforms, from backplanes and optical evaluation boards to high speed test equipment. Each BullsEye connector handles a full GTX Quad, four transmit/receive pairs as well as the two independent reference clocks, enabling the highest level of flexibility in testing custom applications.
Featuring the ROHS compliant VC7203 kit including the XC7VX485T-3FFG1761E FPGA
Logic Cells | 485,760 |
---|---|
DSP Slices | 2,800 |
Memory (Kb) | 37,080 |
GTY 12.5 Gb/s Transceivers | 56 |
I/0 Pins | 700 |
Featuring the VC7203 Characterization Board
Communication & Networking
Clocking
Display
Expansion Connectors
Configuration
Memory
Control & I/O
Power
Featuring the ROHS compliant VC7203 kit including the XC7VX485T-3FFG1761E FPGA
Logic Cells | 485,760 |
---|---|
DSP Slices | 2,800 |
Memory (Kb) | 37,080 |
GTY 12.5 Gb/s Transceivers | 56 |
I/0 Pins | 700 |
Featuring the Virtex-7 XC7VX485T-3FFG1761E FPGA
Node locked & Device-locked to the Virtex-7 XC7VX485T FPGA, with 1 year of updates
10 standard SMAs
Name | Description | License Type |
---|---|---|
Vivado Design Suite Design Edition | The Xilinx Vivado® Design Suite is a revolutionary IP and System Centric design environment built from the ground up to accelerate the design for FPGAs and SoCs. | Node locked & Device-locked to the Virtex-7 XC7VX485T FPGA, with 1 year of updates |