AR# 76244

描述

XPIOL resources for the Versal families are detailed in Chapter 3 of the Versal ACAP SelectIO Architecture Manual (AM010).

These include IDDR, ODDR, single Data rate Flip-flops placed in the IOL known as IFD or OFD and uncalibrated delay elements such as IDELAYE5 and ODELAYE5.

The XPIOL Resources are not available to use in the Vivado 2020.3 release.

Note: this does not impact using the IOB and routing through the IOL and does not impact the HDIO.

Potentially Impacted IP in the 2020.3 release are:

• axi_chip2chip_v5_0
• gig_ethernet_pcs_pma_v16_2
• tri_mode_ethernet_mac_v9_0
• axi_quad_spi_v3_2 - A
• axi_uart16550_v2_0
• gmii_to_rgmii_v4_1

Note that these IP will only be impacted if the selected configuration requires IDDR/ODDR and pins are LOC’ed to an XPIO bank.

There is no impact when HDIO banks are used.

解决方案

If your design is using an unsupported XPIOL you will get the following Warning in Vivado:

[DRC PDRC-262] XPIOLOGIC_resource_use_is_unsupported_in_2020.3: Use of XPIOLOGIC site (XPIOLOGIC_X28Y0) I/O interconnect logic resource by the FDRE cell s1_q_reg is unsupported in the 2020.3 release. Please modify the design by setting the IOB property to FALSE or moving the cell to a fabric SLICE site.

If you need the voltage levels of the XPIO you can try to bypass the XPIOL and capture or drive the data from the PL Fabric.

Note: The issue has been resolved in the 2021.1 Vivado release.