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  3. AR# 50063: 7 Series FPGA GTH Transceiver Initial ES CES9937 Silicon - Link Margin Reduction

AR# 50063

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7 Series FPGA GTH Transceiver Initial ES CES9937 Silicon - Link Margin Reduction

描述

In the 7 Series GTH transceiver Initial ES silicon (CES9937), there can be up to 0.05 UI increase in TX output jitter and 0.05 UI decrease in RX input jitter tolerance for line rates up to 8.5 Gb/s when multiple GTH transceivers are used. Similarly, for line rates higher than 8.5 Gb/s, this can be up to 0.1 UI increase in TX output jitter and 0.1 UI decrease in RX input jitter tolerance when multiple channels are used.

解决方案

Line-rates up to 8.5 Gb/s

If both ends of the link are 7 series FPGAs GTH transceivers, the link margin degradation could be up to 0.1 UI.

Line-rates above 8.5 Gb/s

If both ends of the link are 7 series FPGAs GTH transceivers, the link margin degradation could be up to 0.2 UI.

Supported Use Modes

For GTH transceiver line rates above 8.5 Gb/s and up to 10.3125 Gb/s, the maximum supported channel loss at Nyquist frequency is 25 dB when using the latest DFE attribute settings (PMA_RSV2, RX_BIAS_CFG, RXDFEXYDEN) in (Xilinx Answer 47128). Otherwise, the maximum supported channel loss is 20 dB.

For GTH transceiver line rates above 10.3125 Gb/s and up to 11.3 Gb/s, the maximum supported channel loss at Nyquist frequency is 20 dB.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
47128 Virtex-7 FPGA GTH 收发器的设计咨询——一般工程样品 (ES) 芯片的属性更新、问题和解决方法 N/A N/A
AR# 50063
日期 07/15/2013
状态 Active
Type 综合文章
器件
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