Introduction

The Xilinx® SDAccel™ Development Environment lets you compile OpenCL™ C, C, C++, and RTL kernels to run on Xilinx® programmable platforms. The programmable platform is composed of the SDAccel Xilinx Open Code Compiler (XOCC), a Device Support Archive (DSA) which describes the hardware platform, a software platform, an accelerator board, and the SDAccel OpenCL runtime. The XOCC is a command line compiler that takes user source code and runs it through the Xilinx implementation tools to generate the bitstream and other files that are needed to program the FPGA-based accelerator boards. It supports kernels expressed in OpenCL C, C++, and RTL (SystemVerilog, Verilog, or VHDL).

The majority of this document describes the steps required to create platform designs for use with the SDAccel Development Environment. Platform creation involves configuring the necessary software drivers and runtime software coupled with the hardware platform design and DSA. The hardware platform design provides the physical interface information required for the software kernels to interact with the printed circuit board. These interfaces are captured using Xilinx IP within the Vivado IP integrator environment. Special properties are used to define the boundary of the physical interfaces with the kernel logic coming from the SDx™ Environment. This “shell” is then implemented inside the FPGA with the results stored and reused when each kernel application is implemented. All of the hardware design components are then packaged into the Device Support Archive (DSA) for use with the SDx Environment.

This document is written from the perspective of a hardware designer, using terminology common to the Vivado® Design Suite. An overview of the OpenCL Design flow written from the perspective of a software developer is provided in the SDAccel Environment User Guide (UG1023).