SDSoC Development Environment Changes for 2017.4

The following are changes to existing features in the SDSoC™ Development Environment in this release:

• SDx GUI - The project creation and platform creation process has been updated. This now provides additional functionality to provide for:
  • The ability to create platform projects from within the SDx GUI.
  • The ability to create system projects for multiple SDSoC applications.

• SDSoC sds++ system compiler enhancements.

  • Advanced FPGA control of Vivado through the --xp<Vivado tcl command> option, which allows you to specify Vivado parameters and properties, including Tcl commands and flow pre or post Tcl scripts (the -vpl-ini <file> option, can be used to specify a file containing multiple <parameter_value> options).

  • Accelerator connectivity to streaming IO from FPGA pins can now be specifed with #pragma SDS data sys_port

  • Zynq and Zynq Ultrascale+ base platforms now employ a clock wizard to support up to seven phase aligned clocks.

• System projects for multiple SDSoC applications.
• Streaming IO ports may now be implemented using a simple pragma, sys_port.
• Programmable clocks now specified by a clock wizard.
  • The ZCU102 platform now supports up to seven clocks.

• Support for SDSoC platform creation

  • The SDSoC Platform Utility has been replaced by a first-class platform project type in the SDx GUI.

  • The sdsoc:: namespaced Tcl APIs to declare the hardware platform interface (.hpfm file) have been replaced by Vivado IP Integrator Tcl APIs

  • The SDx GUI now generates a Tcl journal file for batch scripting of platform builds and improved revision control.

  • A platform can now include its own IP cache.

  • The platform hardware handoff from Vivado to the SDx GUI platform project is now generated with the write_dsa command.

  • A migration guide for SDSoC platforms built with prior releases is contained in Appendix D: Migrating SDSoC Platforms of SDSoC Environment Platform Development Guide (UG1146)