Optimizing Kernel Computation

One of the key benefits of FPGA is that you can create custom logic for your specific application. The goal of kernel computation optimization is to create processing logic that can consume all the data as soon as they arrive at kernel interfaces. The key metric during this step is the initiation interval (II). This is generally achieved by expanding the processing code to match the data path with techniques such as function pipelining, loop unrolling, array partitioning, dataflowing, etc. The SDAccel™ Environment produces various compilation reports and profiling data during hardware emulation and system run to assist your optimization effort. Refer to the “Application Profiling in the SDAccel Environment” chapter in the SDAccel Environment User Guide (UG1023) for details on the compilation and profiling report.