After any reset, the debugger hangs when accessing DDR3 memory

Issue

Kintex®-7 FPGA KC705 evaluation board with older device revisions require a workaround during debugging to compensate for the memory controller calibration time, else the debugger freezes.

Solution

For older device revisions, the memory controller requires one to two minutes to calibrate before you can access DDR3 memory. To work around this issue, allow sufficient time for calibration to complete after a reset and disable automatic resets using one of the following methods:
  • When using XMD, after connecting to the target, disable resets running the commands debugconfig -reset_on_run disable and debugconfig -reset_on_data_dow disable.
    Note: XMD has been deprecated and will be removed in future versions of the Xilinx Software Development Kit (SDK). XSDB replaces XMD and provides additional functionality. We recommend you switch to XSDB for command-line debugging.
  • When using SDK, in the debug configuration Device Initialization tab specify the Reset Type value No Reset. Use XMD to perform the reset and wait for the calibration to complete.

See Answer Record 43967 for additional information.