Exporting the RTL Design

The Vitis HLS tool is limited in terms of the estimations it can provide about the RTL design that it generates. It can project resource utilization and timing of the end result, but these are just projections. To get a better view of the RTL design, you can actually run Vivado synthesis and place and route on the generated RTL design, and review actual results of timing and resource utilization. Select the Run Implementation command from the Flow Navigator to open the dialog box as shown below.

The dialog presents the choice of running RTL Synthesis or RTL Synthesis, Place & Route. The dialog box is largely unchanged in either selection, with the exception of the Place & Route Options that appear at the bottom.

RTL

Generate RTL in Verilog or VHDL form.

Clock Period

Specify the clock period, which is defined by the active solution by default.

Generate DCP

Check box to generate a DCP file for the synthesized or implemented design.

IP Location

Specify the location to write the generated IP file.

IP OOC XDC File

Specifies an XDC file to be used for the RTL IP for out-of-context (OOC) synthesis.

IP XDC File

Lets you specify an XDC file for use during Vivado place and route.

Report Level

Defines the report-level generated during synthesis or implementation.

Max Timing Paths

Specify the number of timing paths to extract from the Timing Summary report. The worst case paths are returned as defined by the specified value.

RTL Synthesis Strategy

Specify the strategy to employ in the synthesis run.

Synth Design Arguments

Specify options for the synth_design command.

Run Physical Optimizations

Specify the physical optimization to run. Choices include: none, place, route, and all

Implementation Strategy

Specify the strategy to employ in the implementation run.

The Implementation Report contains the results of Synthesis and Place and Route if it was run. The sections of the report include the following:

General Information

Provides general information related to the design and implementation.

Run Constraints and Options

Reports the constraints and options that were set for the RTL Synthesis run and/or the Place & Route run. This shows you what constraints were set and/or modified for the run.

Resource Usage/Final Timing

The Resource Usage and the Final Timing sections show a quick summary of the resources and timing achieved by either the RTL Synthesis run or the Place & Route run. These sections give a very high-level overview of the resource utilization and status on whether timing goals were met or not. The information in the succeeding sections provide details useful in debugging timing issues.

Resources

A detailed per-module split up of resources is shown in this table. In addition, the tables can also show the original variable and source location information from the source code. If a particular resource was the result of a user-specified pragma, then this can also be shown in the table. This allows you to relate your C code with the synthesized RTL implementation. Inspecting this report is very beneficial because this is after Vivado has synthesized the design and therefore, functional blocks like DSPs and other logic units have all now been instantiated in the circuit.

Fail Fast

The fail fast reports that Vivado provides can guide your investigation into specific issues encountered by the tool. In the fail fast report, you should look into anything with the Status of REVIEW to improve the implementation and timing closure. Different sections of the fail fast report include:

• Design Characteristics: The default utilization guidelines are based on SSI technology devices and can be relaxed for non-SSI technology devices. Designs with one or more REVIEW checks are feasible but are difficult to implement.
• Clocking Checks: These checks are critical and must be addressed.
• LUT and Net Budgeting: Use a conservative method to better predict which logic paths are unlikely to meet timing after placement with high device utilization.

Timing Paths

The Timing Paths reports show the timing critical paths that result in the worst slack for the design. By default, the tool will show the top 10 worst negative slack paths. Each path in the table has detailed information that shows the combination path between one flip-flop to another. Breaking these long combinational paths will be required to address the timing issues. So you need to analyze these paths and reason where they are coming from and map these paths back to the user's C code. Using both these paths and the resources table presented earlier can help in determining and correlating the path back to your source code.

In the figure below, you can see that the top 10 negative slack paths in the Place & Route report actually have higher logic levels (9) as compared to after RTL Synthesis (5), and the max fanout also got worse (64 → 9366). This clearly shows how congestion in the design is causing high logic levels and higher fanouts which in turn causes issues for meeting timing. Using such clues, you can modify your design to remove some of this congestion either by rewriting the C code or making some different design decisions with respect to BRAM/LUTRAM/URAM resource choices.

Vitis HLS writes to the impl folder of the active solution folder when you run the Export RTL command.

The output files and folders include the following:

• component.xml: The IP component file that defines the interfaces and architecture.
• export.zip: The zip archive of the IP and its contents. The zip file can be directly added to the Vivado IP catalog.
• export.xo: The compiled kernel object for use in the Vitis application acceleration development flow.
• impl/ip: The IP contents unzipped.
• impl/ip/example: A folder with a Tcl script used to generate the packaged IP, and a shell script to export the IP.
• impl/report: The report for the synthesized, or placed and routed IP is written to this folder.
• impl/verilog: Contains the Verilog format RTL output files.
• impl/vhdl: Contains the VHDL format RTL output files.
  TIP: If the Vivado synthesis or Vivado synthesis, place, and route options are selected, Vivado synthesis and implementation are performed in the Verilog or VHDL folders. In this case the folder includes a project.xpr file that can be opened in the Vivado Design Suite.

In cases where Vitis HLS uses Xilinx IP in the design, such as with floating point designs, the RTL directory includes a script to create the IP during RTL synthesis. If the files in the verilog or vhdl folders are copied out and used for RTL synthesis, it is your responsibility to correctly use any script files present in those folders. If the package IP is used, this process is performed automatically by the design Xilinx tools. If C/RTL co-simulation has been executed in Vitis HLS, the Vivado project also contains an RTL test bench, and the design can be simulated.

After the project has been completed, and the RTL exported, you can archive the Vitis HLS project to an industry-standard Zip file. Select the File > Archive Project menu command to open the Archive Project dialog box as shown below.

The Archive Project dialog box features the following settings:

• Archive Name: Specifies the name of the archive file to create.
• Active Solution Only: This is selected by default. Disable this option to include all solutions from the current project.
• Include Run Results: By default only the source files and constraints will be included in the archive file. Enable this option to also include the results of simulation and synthesis in the archive file.