Performance and Resource Utilization for Multiply Adder v3.0

Vivado Design Suite Release 2023.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2023.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex-7
Kintex UltraScale
Kintex UltraScale+
Versal ACAP
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Zynq UltraScale+

Kintex-7

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_a_width	c_b_width	c_c_width	c_out_high	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k70t	fbv676	1	k7_1_24x17_47	24	17	47	47	CLK	544	0	0	1	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_35x17_47	35	17	47	52	CLK	544	0	18	2	0	0	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_a_width	c_b_width	c_c_width	c_out_high	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku025	ffva1156	1	ku_1_24x17_47	24	17	47	47	CLK	631	0	0	1	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_35x17_47	35	17	47	52	CLK	631	0	18	2	0	0	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_a_width	c_b_width	c_c_width	c_out_high	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku11p	ffva1156	1	kup_1_24x17_47	24	17	47	47	CLK	866	0	0	1	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_35x17_47	35	17	47	52	CLK	833	0	18	2	0	0	PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_a_width	c_b_width	c_c_width	c_out_high	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	1LP	ver_1_24x17_47	24	17	47	47	CLK	680	0	0	1	0	0	PRODUCTION 2.11 2022-11-23
xcvc1902	vsva2197	1LP	ver_1_35x17_47	35	17	47	52	CLK	680	0	18	2	0	0	PRODUCTION 2.11 2022-11-23

Virtex-7

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_a_width	c_b_width	c_c_width	c_out_high	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1157	1	v7_1_24x17_47	24	17	47	47	CLK	544	0	0	1	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_35x17_47	35	17	47	52	CLK	544	0	18	2	0	0	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_a_width	c_b_width	c_c_width	c_out_high	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu065	ffvc1517	1	vu_1_24x17_47	24	17	47	47	CLK	631	0	0	1	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_35x17_47	35	17	47	52	CLK	631	0	18	2	0	0	PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_a_width	c_b_width	c_c_width	c_out_high	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu11p	flga2577	1	vup_1_24x17_47	24	17	47	47	CLK	866	0	0	1	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_35x17_47	35	17	47	52	CLK	833	0	18	2	0	0	PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_a_width	c_b_width	c_c_width	c_out_high	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	1LV	zup_1_24x17_47	24	17	47	47	CLK	774	0	0	1	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_35x17_47	35	17	47	52	CLK	680	0	18	2	0	0	PRODUCTION 1.30 05-15-2022

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