Resource Utilization for Video DisplayPort 1.4 RX Subsystem v3.0

Vivado Design Suite Release 2021.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2021.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Versal ACAP
Zynq UltraScale+

Versal ACAP

Part Information			Configuration Parameters																	Resource Utilization
Device	Package	Speed Grade	Configuration Name	MODE	PHY_DATA_WIDTH	BITS_PER_COLOR	NUM_STREAMS	LANE_COUNT	AUDIO_ENABLE	AUDIO_CHANNELS	AUX_IO_LOC	AUX_IO_TYPE	HDCP_ENABLE	HDCP22_ENABLE	VIDEO_INTERFACE	PIXEL_MODE	EDP_ENABLE	LINK_RATE	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	MMCM	BUFGCE	URAM	Speedfile Status
xcvc1902	vsva2197	3HP	versal_default	0	2	8	1	1	0	2	0	0	0	0	0	1	0	8.1	m_axis_aclk_stream1=300 rx_dec_clk=405 rx_lnk_clk=506 rx_vid_clk=300 s_axi_aclk=100	6306	7122	0	4	1	0	5	0	ENGINEERING-SAMPLE 2.01 2021-05-28

Zynq UltraScale+

Part Information			Configuration Parameters																	Resource Utilization
Device	Package	Speed Grade	Configuration Name	MODE	PHY_DATA_WIDTH	BITS_PER_COLOR	NUM_STREAMS	LANE_COUNT	AUDIO_ENABLE	AUDIO_CHANNELS	AUX_IO_LOC	AUX_IO_TYPE	HDCP_ENABLE	HDCP22_ENABLE	VIDEO_INTERFACE	PIXEL_MODE	EDP_ENABLE	LINK_RATE	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	MMCM	PLL	BUFGCE	Speedfile Status
xczu9eg	ffvb1156	-2	test_1__rx	0	2	8		1	0			0	0		0	1			m_axis_aclk_stream1=300 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100	6161	6738	0	4	1	0	0	1	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_2__rx	0	2	8		4	1	2		0	0		0	4			m_aud_axis_aclk=25 m_axis_aclk_stream1=300 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100	11416	12771	0	5	2	0	0	1	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_3__rx	0	2	8		1	1	4		0	1		0	1			hdcp_ext_clk=203 m_aud_axis_aclk=25 m_axis_aclk_stream1=300 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100	15166	14079	0	7	2	0	0	1	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_4__rx	0	2	10		4	1	4		0	1		0	4			hdcp_ext_clk=203 m_aud_axis_aclk=25 m_axis_aclk_stream1=300 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100	21187	20021	0	8	2	0	0	1	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_5__rx	0	2	16		4	1	4		0	1	1	0	4			hdcp_ext_clk=203 m_aud_axis_aclk=25 m_axis_aclk_stream1=300 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100	37222	29826	5	15	3	0	0	1	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_6__rx	0	2	16		1	0			0	1		0	1			hdcp_ext_clk=203 m_axis_aclk_stream1=300 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100	14549	12773	0	9	1	0	0	1	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_7__rx	1	2	12		1	1	5		0	0		0	4			m_aud_axis_aclk=25 m_axis_aclk_stream1=300 m_axis_aclk_stream2=300 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100	21129	22430	0	11	3	0	0	1	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_8__rx	1	2	16		2	1	2		0	0		1	4			m_aud_axis_aclk=25 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100	20008	21770	0	1	1	0	0	1	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-2	test_9__rx	1	2	10		4	0			0	0		1	4			rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100	18356	19235	0	0	0	0	0	1	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	-3	uplus_default	0	2	8	1	1	0	2	0	0	0	0	0	1	0	8.1	m_axis_aclk_stream1=300 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100	6156	6738	0	4	1	0	0	1	PRODUCTION 1.29 08-03-2020

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