Resource Utilization for MIPI CSI-2 Rx Subsystem v5.1

Vivado Design Suite Release 2021.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2021.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex-7
Zynq UltraScale+

Kintex-7

Part Information			Configuration Parameters						Resource Utilization
Device	Package	Speed Grade	Configuration Name	VFB_TU_WIDTH	CMN_PXL_FORMAT	CMN_NUM_LANES	DPY_EN_REG_IF	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k325t	ffg900	2	mipi_config_4		YUV422_8bit	2	false	dphy_clk_200M=200 lite_aclk=100 mipi_phy_if_clk_hs_p=400 video_aclk=150	2326	3604	0	4	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	mipi_config_default_7series		RAW8	1	false	dphy_clk_200M=200 lite_aclk=100 mipi_phy_if_clk_hs_p=400 video_aclk=150	1935	2853	0	2	0	PRODUCTION 1.12 2017-02-17

Zynq UltraScale+

Part Information			Configuration Parameters						Resource Utilization
Device	Package	Speed Grade	Configuration Name	VFB_TU_WIDTH	CMN_PXL_FORMAT	CMN_NUM_LANES	DPY_EN_REG_IF	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	2	mipi_config_0	1				clkoutphy_in=800 dphy_clk_200M=200 lite_aclk=100 mipi_phy_if_clk_p=400 video_aclk=150	2035	2908	0	2	0	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	2	mipi_config_1		RAW10	2	false	clkoutphy_in=800 dphy_clk_200M=200 lite_aclk=100 mipi_phy_if_clk_p=400 video_aclk=150	2608	3815	0	4	0	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	2	mipi_config_2		RGB888	3	false	clkoutphy_in=800 dphy_clk_200M=200 lite_aclk=100 mipi_phy_if_clk_p=400 video_aclk=150	2844	4289	0	4	0	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	2	mipi_config_3		YUV422_8bit	4	false	clkoutphy_in=800 dphy_clk_200M=200 lite_aclk=100 mipi_phy_if_clk_p=400 video_aclk=150	2837	4087	0	4	0	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	2	mipi_config_default		RAW8	1	false	clkoutphy_in=800 dphy_clk_200M=200 lite_aclk=100 mipi_phy_if_clk_p=400 video_aclk=150	2035	2908	0	2	0	PRODUCTION 1.29 08-03-2020

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