Performance and Resource Utilization for Discrete Fourier Transform v4.2

Vivado Design Suite Release 2021.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2021.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex-7
Kintex UltraScale
Kintex UltraScale+
Versal ACAP
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Zynq UltraScale+

Kintex-7

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k70t	fbv676	1	k7_1_d16_area_1536	16	Area	false		true	CLK	341	3635	4699	16	4	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_area_5g	16	Area	false	true	true	CLK	172	3740	4842	16	10	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_area_no1536	16	Area	false		false	CLK	341	3637	4669	16	3	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_spd_1536	16	Speed	false		true	CLK	341	3635	4699	16	4	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_spd_5g	16	Speed	false	true	true	CLK	172	3740	4842	16	10	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_spd_no1536	16	Speed	false		false	CLK	341	3637	4669	16	3	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d8_area_1536	8	Area	false		true	CLK	341	2900	3622	16	4	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d8_area_5g	8	Area	false	true	true	CLK	166	3093	3766	16	10	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d8_area_no1536	8	Area	false		false	CLK	352	2906	3607	16	3	4	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku025	ffva1156	1	ku_1_d16_area_1536	16	Area	false		true	CLK	407	3533	4684	16	4	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_area_5g	16	Area	false	true	true	CLK	402	3892	4970	16	10	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_area_no1536	16	Area	false		false	CLK	402	3545	4786	16	3	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_spd_1536	16	Speed	false		true	CLK	407	3533	4684	16	4	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_spd_5g	16	Speed	false	true	true	CLK	402	3892	4970	16	10	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_spd_no1536	16	Speed	false		false	CLK	402	3545	4786	16	3	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d8_area_1536	8	Area	false		true	CLK	402	2883	3760	16	4	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d8_area_5g	8	Area	false	true	true	CLK	407	3207	3881	16	10	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d8_area_no1536	8	Area	false		false	CLK	407	2900	3578	16	3	4	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku11p	ffva1156	1	kup_1_d16_area_1536	16	Area	false		true	CLK	560	3826	5069	16	4	4	PRODUCTION 1.28 02-27-2020
xcku11p	ffva1156	1	kup_1_d16_area_5g	16	Area	false	true	true	CLK	560	4154	5116	16	10	0	PRODUCTION 1.28 02-27-2020
xcku11p	ffva1156	1	kup_1_d16_area_no1536	16	Area	false		false	CLK	560	3855	4978	16	3	4	PRODUCTION 1.28 02-27-2020
xcku11p	ffva1156	1	kup_1_d16_spd_1536	16	Speed	false		true	CLK	560	3826	5069	16	4	4	PRODUCTION 1.28 02-27-2020
xcku11p	ffva1156	1	kup_1_d16_spd_5g	16	Speed	false	true	true	CLK	560	4154	5116	16	10	0	PRODUCTION 1.28 02-27-2020
xcku11p	ffva1156	1	kup_1_d16_spd_no1536	16	Speed	false		false	CLK	560	3855	4978	16	3	4	PRODUCTION 1.28 02-27-2020
xcku11p	ffva1156	1	kup_1_d8_area_1536	8	Area	false		true	CLK	566	3115	3725	16	4	4	PRODUCTION 1.28 02-27-2020
xcku11p	ffva1156	1	kup_1_d8_area_5g	8	Area	false	true	true	CLK	560	3430	3886	16	10	0	PRODUCTION 1.28 02-27-2020
xcku11p	ffva1156	1	kup_1_d8_area_no1536	8	Area	false		false	CLK	566	3148	3583	16	3	4	PRODUCTION 1.28 02-27-2020

Versal ACAP

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	1LP	ver_1_d16_area_1536	16	Area	false		true	CLK	440	3479	4618	16	4	4	PRODUCTION 2.03 2021-08-23
xcvc1902	vsva2197	1LP	ver_1_d16_area_5g	16	Area	false	true	true	CLK	440	3861	5152	16	10	0	PRODUCTION 2.03 2021-08-23
xcvc1902	vsva2197	1LP	ver_1_d16_area_no1536	16	Area	false		false	CLK	440	3480	5018	16	3	4	PRODUCTION 2.03 2021-08-23
xcvc1902	vsva2197	1LP	ver_1_d16_spd_1536	16	Speed	false		true	CLK	440	3479	4618	16	4	4	PRODUCTION 2.03 2021-08-23
xcvc1902	vsva2197	1LP	ver_1_d16_spd_5g	16	Speed	false	true	true	CLK	440	3861	5152	16	10	0	PRODUCTION 2.03 2021-08-23
xcvc1902	vsva2197	1LP	ver_1_d16_spd_no1536	16	Speed	false		false	CLK	440	3480	5018	16	3	4	PRODUCTION 2.03 2021-08-23
xcvc1902	vsva2197	1LP	ver_1_d8_area_1536	8	Area	false		true	CLK	440	2849	4046	16	4	4	PRODUCTION 2.03 2021-08-23
xcvc1902	vsva2197	1LP	ver_1_d8_area_5g	8	Area	false	true	true	CLK	440	3193	3917	16	10	0	PRODUCTION 2.03 2021-08-23
xcvc1902	vsva2197	1LP	ver_1_d8_area_no1536	8	Area	false		false	CLK	440	2859	3834	16	3	4	PRODUCTION 2.03 2021-08-23

Virtex-7

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1157	1	v7_1_d16_area_1536	16	Area	false		true	CLK	336	3599	4624	16	4	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_area_5g	16	Area	false	true	true	CLK	177	3746	4842	16	10	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_area_no1536	16	Area	false		false	CLK	341	3634	4613	16	3	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_spd_1536	16	Speed	false		true	CLK	336	3599	4624	16	4	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_spd_5g	16	Speed	false	true	true	CLK	177	3746	4842	16	10	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_spd_no1536	16	Speed	false		false	CLK	341	3634	4613	16	3	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d8_area_1536	8	Area	false		true	CLK	347	2905	3546	16	4	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d8_area_5g	8	Area	false	true	true	CLK	177	3093	3766	16	10	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d8_area_no1536	8	Area	false		false	CLK	347	2907	3545	16	3	4	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu065	ffvc1517	1	vu_1_d16_area_1536	16	Area	false		true	CLK	407	3538	4732	16	4	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_area_5g	16	Area	false	true	true	CLK	402	3873	5016	16	10	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_area_no1536	16	Area	false		false	CLK	402	3543	4928	16	3	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_spd_1536	16	Speed	false		true	CLK	407	3538	4732	16	4	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_spd_5g	16	Speed	false	true	true	CLK	402	3873	5016	16	10	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_spd_no1536	16	Speed	false		false	CLK	402	3543	4928	16	3	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d8_area_1536	8	Area	false		true	CLK	407	2924	3733	16	4	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d8_area_5g	8	Area	false	true	true	CLK	396	3211	3805	16	10	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d8_area_no1536	8	Area	false		false	CLK	407	2909	3776	16	3	4	PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu11p	flga2577	1	vup_1_d16_area_1536	16	Area	false		true	CLK	566	3857	5125	16	4	4	PRODUCTION 1.27 02-28-2020
xcvu11p	flga2577	1	vup_1_d16_area_5g	16	Area	false	true	true	CLK	555	4131	5033	16	10	0	PRODUCTION 1.27 02-28-2020
xcvu11p	flga2577	1	vup_1_d16_area_no1536	16	Area	false		false	CLK	566	3861	4958	16	3	4	PRODUCTION 1.27 02-28-2020
xcvu11p	flga2577	1	vup_1_d16_spd_1536	16	Speed	false		true	CLK	566	3857	5125	16	4	4	PRODUCTION 1.27 02-28-2020
xcvu11p	flga2577	1	vup_1_d16_spd_5g	16	Speed	false	true	true	CLK	555	4131	5033	16	10	0	PRODUCTION 1.27 02-28-2020
xcvu11p	flga2577	1	vup_1_d16_spd_no1536	16	Speed	false		false	CLK	566	3861	4958	16	3	4	PRODUCTION 1.27 02-28-2020
xcvu11p	flga2577	1	vup_1_d8_area_1536	8	Area	false		true	CLK	566	3111	3583	16	4	4	PRODUCTION 1.27 02-28-2020
xcvu11p	flga2577	1	vup_1_d8_area_5g	8	Area	false	true	true	CLK	566	3431	4025	16	10	0	PRODUCTION 1.27 02-28-2020
xcvu11p	flga2577	1	vup_1_d8_area_no1536	8	Area	false		false	CLK	555	3086	3818	16	3	4	PRODUCTION 1.27 02-28-2020

Zynq UltraScale+

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	1LV	zup_1_d16_area_1536	16	Area	false		true	CLK	456	3629	5032	16	4	4	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	1LV	zup_1_d16_area_5g	16	Area	false	true	true	CLK	435	3820	5181	16	10	0	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	1LV	zup_1_d16_area_no1536	16	Area	false		false	CLK	456	3600	5040	16	3	4	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	1LV	zup_1_d16_spd_1536	16	Speed	false		true	CLK	456	3629	5032	16	4	4	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	1LV	zup_1_d16_spd_5g	16	Speed	false	true	true	CLK	435	3820	5181	16	10	0	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	1LV	zup_1_d16_spd_no1536	16	Speed	false		false	CLK	456	3600	5040	16	3	4	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	1LV	zup_1_d8_area_1536	8	Area	false		true	CLK	456	2886	3887	16	4	4	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	1LV	zup_1_d8_area_5g	8	Area	false	true	true	CLK	450	3210	4010	16	10	0	PRODUCTION 1.29 08-03-2020
xczu9eg	ffvb1156	1LV	zup_1_d8_area_no1536	8	Area	false		false	CLK	456	2904	3871	16	3	4	PRODUCTION 1.29 08-03-2020

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Copyright 2021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

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