Performance and Resource Utilization for Binary Counter v12.0

Vivado Design Suite Release 2023.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbv676 1 k7_1_128_lut Fabric 128 false 1 UP false 8 CLK 636 160 270 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 615 209 518 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 308 199 337 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_18_lut Fabric 18 false 1 UP false 2 CLK 817 22 30 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 691 22 30 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_47_lut Fabric 47 false 1 UP false 2 CLK 642 25 73 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_48_dsp DSP48 48 false 1 UP false 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 374 8 0 1 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku025 ffva1156 1 ku_1_128_lut Fabric 128 false 1 UP false 8 CLK 669 177 271 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 669 209 502 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 369 199 309 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_18_lut Fabric 18 false 1 UP false 2 CLK 1063 20 29 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 702 22 30 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_47_lut Fabric 47 false 1 UP false 2 CLK 741 25 74 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_48_dsp DSP48 48 false 1 UP false 2 CLK 675 0 0 1 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 631 0 0 1 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 429 8 0 1 0 0 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffva1156 1 kup_1_128_lut Fabric 128 false 1 UP false 8 CLK 872 175 270 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 872 209 494 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 544 200 357 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1413 19 29 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 1150 22 30 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_47_lut Fabric 47 false 1 UP false 2 CLK 1030 25 73 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 833 0 0 1 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 833 0 0 1 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 625 8 0 1 0 0 PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP ver_1_128_lut Fabric 128 false 1 UP false 8 CLK 680 215 270 0 0 0 PRODUCTION 2.11 2022-11-23
xcvc1902 vsva2197 1LP ver_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 669 267 495 0 0 0 PRODUCTION 2.11 2022-11-23
xcvc1902 vsva2197 1LP ver_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 413 258 391 0 0 0 PRODUCTION 2.11 2022-11-23
xcvc1902 vsva2197 1LP ver_1_18_lut Fabric 18 false 1 UP false 2 CLK 680 19 29 0 0 0 PRODUCTION 2.11 2022-11-23
xcvc1902 vsva2197 1LP ver_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 680 23 30 0 0 0 PRODUCTION 2.11 2022-11-23
xcvc1902 vsva2197 1LP ver_1_47_lut Fabric 47 false 1 UP false 2 CLK 680 50 73 0 0 0 PRODUCTION 2.11 2022-11-23
xcvc1902 vsva2197 1LP ver_1_48_dsp DSP48 48 false 1 UP false 2 CLK 680 0 0 1 0 0 PRODUCTION 2.11 2022-11-23
xcvc1902 vsva2197 1LP ver_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 680 0 0 1 0 0 PRODUCTION 2.11 2022-11-23
xcvc1902 vsva2197 1LP ver_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 396 16 0 1 0 0 PRODUCTION 2.11 2022-11-23

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1157 1 v7_1_128_lut Fabric 128 false 1 UP false 8 CLK 636 160 270 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 631 209 522 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 292 199 325 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_18_lut Fabric 18 false 1 UP false 2 CLK 790 23 30 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 730 22 30 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_47_lut Fabric 47 false 1 UP false 2 CLK 680 25 74 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_48_dsp DSP48 48 false 1 UP false 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 363 8 0 1 0 0 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 1 vu_1_128_lut Fabric 128 false 1 UP false 8 CLK 691 176 270 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 669 209 495 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 369 199 305 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_18_lut Fabric 18 false 1 UP false 2 CLK 1074 21 29 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 658 22 30 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_47_lut Fabric 47 false 1 UP false 2 CLK 713 25 73 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_48_dsp DSP48 48 false 1 UP false 2 CLK 675 0 0 1 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 631 0 0 1 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 429 8 0 1 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 vup_1_128_lut Fabric 128 false 1 UP false 8 CLK 872 176 270 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 872 209 494 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 516 199 357 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1277 19 29 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 1156 22 30 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_47_lut Fabric 47 false 1 UP false 2 CLK 1047 25 73 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 833 0 0 1 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 833 0 0 1 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 615 8 0 1 0 0 PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 1LV zup_1_128_lut Fabric 128 false 1 UP false 8 CLK 636 176 270 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 636 209 494 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 402 199 345 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1041 21 29 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 839 22 30 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_47_lut Fabric 47 false 1 UP false 2 CLK 806 25 73 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 768 0 0 1 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 768 0 0 1 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 456 8 0 1 0 0 PRODUCTION 1.30 05-15-2022

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