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rules,properties values,syntax examples application/pdf Vivado Design Suite Properties Reference Guide Xilinx, Inc. Documents the properties available for use in the Vivado® Design Suite. For each property this manual provides a description; supported Xilinx® FPGA devices; applicable logic elements or device resources; accepted values; Verilog, VHDL, and XDC syntax examples; and affected FPGA design flow steps. 2013-2021 uuid:438d47da-0aaf-4fa8-862e-0350c0c0a5c0 uuid:a5c3d840-fafc-4f3d-864e-5097a5733dc0 2021-12-03T16:08:35+05:30 endstream endobj 15749 0 obj << /Author (Xilinx, Inc.) /Copyright (2013-2021) /CreationDate (D:20211203133346Z) /Creator (FrameMaker 2019.0.5) /Keywords (ug912,Virtex,Kintex,Artix,properties,Xilinx Design constraints,XDC,XDC properties,architecture suppor\ t, applicable elements,propagation rules,properties values,syntax examples) /ModDate (D:20211203160835+05'30') /PostProcess (v2021.2.0.1) /Producer (Xilinx, Inc. via ABCpdf) /Subject (Documents the properties available for use in the Vivado Design Suite. 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/Parent 16665 0 R /Title (XDC Syntax Example) >> endobj 16669 0 obj << /Dest (G5.608241) /Next 16665 0 R /Parent 16663 0 R /Prev 16664 0 R /Title (VHDL Syntax) >> endobj 16670 0 obj << /Dest (G5.688398) /Next 15816 0 R /Parent 15814 0 R /Prev 16671 0 R /Title (Affected Steps) >> endobj 16671 0 obj << /Count -3 /Dest (G5.688381) /First 16672 0 R /Last 16673 0 R /Next 16670 0 R /Parent 15814 0 R /Prev 16674 0 R /Title (Syntax) >> endobj 16672 0 obj << /Dest (G5.688384) /Next 16676 0 R /Parent 16671 0 R /Title (Verilog Syntax) >> endobj 16673 0 obj << /Dest (G5.688392) /Parent 16671 0 R /Prev 16676 0 R /Title (XDC Syntax) >> endobj 16674 0 obj << /Dest (G5.688380) /Next 16671 0 R /Parent 15814 0 R /Prev 16675 0 R /Title (Values) >> endobj 16675 0 obj << /Dest (G5.688378) /Next 16674 0 R /Parent 15814 0 R /Prev 15815 0 R /Title (Applicable Objects) >> endobj 16676 0 obj << /Dest (G5.688387) /Next 16673 0 R /Parent 16671 0 R /Prev 16672 0 R /Title (VHDL Syntax) >> endobj 16677 0 obj << /Dest (G5.689707) /Next 15813 0 R /Parent 15811 0 R /Prev 16678 0 R /Title (Affected Steps) >> endobj 16678 0 obj << /Count -3 /Dest (G5.689311) /First 16679 0 R /Last 16680 0 R /Next 16677 0 R /Parent 15811 0 R /Prev 16681 0 R /Title (Syntax) >> endobj 16679 0 obj << /Dest (G5.689312) /Next 16683 0 R /Parent 16678 0 R /Title (Verilog Syntax) >> endobj 16680 0 obj << /Dest (G5.689420) /Parent 16678 0 R /Prev 16683 0 R /Title (XDC Syntax) >> endobj 16681 0 obj << /Dest (G5.689233) /Next 16678 0 R /Parent 15811 0 R /Prev 16682 0 R /Title (Values) >> endobj 16682 0 obj << /Dest (G5.689692) /Next 16681 0 R /Parent 15811 0 R /Prev 15812 0 R /Title (Applicable Objects) >> endobj 16683 0 obj << /Dest (G5.689384) /Next 16680 0 R /Parent 16678 0 R /Prev 16679 0 R /Title (VHDL Syntax) >> endobj 16684 0 obj << /Dest (G5.998532) /Next 15810 0 R /Parent 15808 0 R /Prev 16685 0 R /Title (Affected Steps) >> endobj 16685 0 obj << /Dest (G5.998495) /Next 16684 0 R /Parent 15808 0 R /Prev 16686 0 R /Title (Syntax) >> endobj 16686 0 obj << /Dest (G5.998459) /Next 16685 0 R /Parent 15808 0 R /Prev 16687 0 R /Title (Values) >> endobj 16687 0 obj << /Dest (G5.998430) /Next 16686 0 R /Parent 15808 0 R /Prev 15809 0 R /Title (Applicable Objects) >> endobj 16688 0 obj << /Dest (G5.488513) /Next 15807 0 R /Parent 15805 0 R /Prev 16689 0 R /Title (Syntax) >> endobj 16689 0 obj << /Dest (G5.488511) /Next 16688 0 R /Parent 15805 0 R /Prev 16690 0 R /Title (Values) >> endobj 16690 0 obj << /Dest (G5.488509) /Next 16689 0 R /Parent 15805 0 R /Prev 15806 0 R /Title (Applicable Objects) >> endobj 16691 0 obj << /Dest (G5.478453) /Next 15804 0 R /Parent 15802 0 R /Prev 16692 0 R /Title (Syntax) >> endobj 16692 0 obj << /Dest (G5.478451) /Next 16691 0 R /Parent 15802 0 R /Prev 16693 0 R /Title (Values) >> endobj 16693 0 obj << /Dest (G5.478448) /Next 16692 0 R /Parent 15802 0 R /Prev 15803 0 R /Title (Applicable Objects) >> endobj 16694 0 obj << /Dest (G5.793073) /Next 15801 0 R /Parent 15799 0 R /Prev 16695 0 R /Title (Affected Steps) >> endobj 16695 0 obj << /Count -3 /Dest (G5.793061) /First 16696 0 R /Last 16697 0 R /Next 16694 0 R /Parent 15799 0 R /Prev 16698 0 R /Title (Syntax) >> endobj 16696 0 obj << /Dest (G5.793063) /Next 16700 0 R /Parent 16695 0 R /Title (Verilog and VHDL Syntax) >> endobj 16697 0 obj << /Dest (G5.793070) /Parent 16695 0 R /Prev 16700 0 R /Title (XDC Example:) >> endobj 16698 0 obj << /Dest (G5.793057) /Next 16695 0 R /Parent 15799 0 R /Prev 16699 0 R /Title (Value) >> endobj 16699 0 obj << /Dest (G5.793054) /Next 16698 0 R /Parent 15799 0 R /Prev 15800 0 R /Title (Applicable Objects) >> endobj 16700 0 obj << /Dest (G5.793066) /Next 16697 0 R /Parent 16695 0 R /Prev 16696 0 R /Title (XDC Syntax) >> endobj 16701 0 obj << /Dest (G5.455321) /Next 15798 0 R /Parent 15796 0 R /Prev 16702 0 R /Title (Affected Steps) >> endobj 16702 0 obj << /Count -3 /Dest (G5.435036) /First 16703 0 R /Last 16704 0 R /Next 16701 0 R /Parent 15796 0 R /Prev 16705 0 R /Title (Syntax) >> endobj 16703 0 obj << /Count -1 /Dest (G5.456313) /First 16708 0 R /Last 16708 0 R /Next 16707 0 R /Parent 16702 0 R /Title (Verilog Syntax) >> endobj 16704 0 obj << /Dest (G5.455472) /Parent 16702 0 R /Prev 16707 0 R /Title (XDC Syntax) >> endobj 16705 0 obj << /Dest (G5.435032) /Next 16702 0 R /Parent 15796 0 R /Prev 16706 0 R /Title (Values) >> endobj 16706 0 obj << /Dest (G5.435027) /Next 16705 0 R /Parent 15796 0 R /Prev 15797 0 R /Title (Applicable Objects) >> endobj 16707 0 obj << /Dest (G5.456264) /Next 16704 0 R /Parent 16702 0 R /Prev 16703 0 R /Title (VHDL Syntax) >> endobj 16708 0 obj << /Dest (G5.456207) /Parent 16703 0 R /Title (Verilog Example) >> endobj 16709 0 obj << /Dest (G5.455279) /Next 15795 0 R /Parent 15793 0 R /Prev 16710 0 R /Title (Affected Steps) >> endobj 16710 0 obj << /Count -2 /Dest (G5.455277) /First 16711 0 R /Last 16712 0 R /Next 16709 0 R /Parent 15793 0 R /Prev 16713 0 R /Title (Syntax) >> endobj 16711 0 obj << /Dest (G5.597099) /Next 16712 0 R /Parent 16710 0 R /Title (Verilog and VHDL Syntax) >> endobj 16712 0 obj << /Count -1 /Dest (G5.461977) /First 16715 0 R /Last 16715 0 R /Parent 16710 0 R /Prev 16711 0 R /Title (XDC Syntax) >> endobj 16713 0 obj << /Dest (G5.455273) /Next 16710 0 R /Parent 15793 0 R /Prev 16714 0 R /Title (Values) >> endobj 16714 0 obj << /Dest (G5.455268) /Next 16713 0 R /Parent 15793 0 R /Prev 15794 0 R /Title (Applicable Objects) >> endobj 16715 0 obj << /Dest (G5.461963) /Parent 16712 0 R /Title (XDC Example) >> endobj 16716 0 obj << /Dest (G5.459319) /Next 15792 0 R /Parent 15790 0 R /Prev 16717 0 R /Title (Affected Steps) >> endobj 16717 0 obj << /Count -3 /Dest (G5.435087) /First 16718 0 R /Last 16719 0 R /Next 16716 0 R /Parent 15790 0 R /Prev 16720 0 R /Title (Syntax) >> endobj 16718 0 obj << /Count -1 /Dest (G5.459232) /First 16723 0 R /Last 16723 0 R /Next 16722 0 R /Parent 16717 0 R /Title (Verilog Syntax) >> endobj 16719 0 obj << /Dest (G5.459312) /Parent 16717 0 R /Prev 16722 0 R /Title (XDC Syntax) >> endobj 16720 0 obj << /Dest (G5.459119) /Next 16717 0 R /Parent 15790 0 R /Prev 16721 0 R /Title (Values) >> endobj 16721 0 obj << /Dest (G5.435078) /Next 16720 0 R /Parent 15790 0 R /Prev 15791 0 R /Title (Applicable Objects) >> endobj 16722 0 obj << /Dest (G5.459303) /Next 16719 0 R /Parent 16717 0 R /Prev 16718 0 R /Title (VHDL Syntax) >> endobj 16723 0 obj << /Dest (G5.459235) /Parent 16718 0 R /Title (Verilog Example) >> endobj 16724 0 obj << /Dest (G5.434512) /Next 15789 0 R /Parent 17184 0 R /Prev 16725 0 R /Title (Syntax) >> endobj 16725 0 obj << /Dest (G5.434509) /Next 16724 0 R /Parent 17184 0 R /Prev 16726 0 R /Title (Values) >> endobj 16726 0 obj << /Dest (G5.434504) /Next 16725 0 R /Parent 17184 0 R /Prev 15788 0 R /Title (Applicable Objects) >> endobj 16727 0 obj << /Dest (G5.466765) /Next 17183 0 R /Parent 17181 0 R /Prev 16728 0 R /Title (Syntax) >> endobj 16728 0 obj << /Dest (G5.434848) /Next 16727 0 R /Parent 17181 0 R /Prev 16729 0 R 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(G5.630987) /First 16738 0 R /Last 16738 0 R /Parent 17327 0 R /Prev 16736 0 R /Title (XDC Syntax) >> endobj 16738 0 obj << /Dest (G5.630991) /Parent 16737 0 R /Title (XDC Syntax Example) >> endobj 16739 0 obj << /Count -1 /Dest (G5.387769) /First 16744 0 R /Last 16744 0 R /Next 16742 0 R /Parent 17331 0 R /Title (Verilog Syntax) >> endobj 16740 0 obj << /Count -1 /Dest (G5.366759) /First 16741 0 R /Last 16741 0 R /Parent 17331 0 R /Prev 16742 0 R /Title (XDC Syntax) >> endobj 16741 0 obj << /Dest (G5.386051) /Parent 16740 0 R /Title (XDC Syntax Example) >> endobj 16742 0 obj << /Count -1 /Dest (G5.366726) /First 16743 0 R /Last 16743 0 R /Next 16740 0 R /Parent 17331 0 R /Prev 16739 0 R /Title (VHDL Syntax) >> endobj 16743 0 obj << /Dest (G5.366734) /Parent 16742 0 R /Title (VHDL Syntax Example) >> endobj 16744 0 obj << /Dest (G5.366704) /Parent 16739 0 R /Title (Verilog Syntax Example) >> endobj 16745 0 obj << /Dest (G5.793232) /Next 17337 0 R /Parent 17335 0 R /Prev 17336 0 R /Title (XDC Syntax) >> endobj 16746 0 obj [1895 0 R /XYZ 92 709 0] endobj 16747 0 obj [2246 0 R /XYZ 92 709 0] endobj 16748 0 obj [2400 0 R /XYZ 92 709 0] endobj 16749 0 obj [2533 0 R /XYZ 92 709 0] endobj 16750 0 obj [3293 0 R /XYZ 92 709 0] endobj 16751 0 obj [3317 0 R /XYZ 92 709 0] endobj 16752 0 obj [3409 0 R /XYZ 92 709 0] endobj 16753 0 obj [3445 0 R /XYZ 92 709 0] endobj 16754 0 obj [3445 0 R /XYZ 92 709 0] endobj 16755 0 obj [3559 0 R /XYZ 92 709 0] endobj 16756 0 obj [1528 0 R /XYZ 92 709 0] endobj 16757 0 obj [4102 0 R /XYZ 92 709 0] endobj 16758 0 obj [4102 0 R /XYZ 92 709 0] endobj 16759 0 obj [5045 0 R /XYZ 92 709 0] endobj 16760 0 obj [5045 0 R /XYZ 92 709 0] endobj 16761 0 obj [432 0 R /XYZ 92 584 0] endobj 16762 0 obj [464 0 R /XYZ 92 709 0] endobj 16763 0 obj [486 0 R /XYZ 92 709 0] endobj 16764 0 obj [509 0 R /XYZ 92 709 0] endobj 16765 0 obj [533 0 R /XYZ 92 709 0] endobj 16766 0 obj [566 0 R /XYZ 92 709 0] endobj 16767 0 obj [589 0 R /XYZ 92 709 0] endobj 16768 0 obj [611 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