From ef8a7ede28ac5c77faa6fb891c14cd294384b7dd Mon Sep 17 00:00:00 2001 From: Pallav Joshi Date: Tue, 16 May 2017 13:07:12 +0530 Subject: [PATCH] zynqmp_pmufw: Bypass RPLL in system reset for Silicon 1.0 Workaround for a bug in 1.0 silicon Signed-off-by: Pallav Joshi Acked-by: Jyotheeswar Reddy Mutthareddyvari --- lib/sw_apps/zynqmp_pmufw/src/pm_core.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_core.c b/lib/sw_apps/zynqmp_pmufw/src/pm_core.c index 0077138..54c1126 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/pm_core.c +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_core.c @@ -51,6 +51,7 @@ #include "pm_clock.h" #include "pm_requirement.h" #include "pm_config.h" +#include "xpfw_platform.h" #include "xpfw_resets.h" #include "rpu.h" #include "xsecure.h" @@ -786,6 +787,12 @@ static void PmSystemShutdown(PmMaster* const master, const u32 type, XPfw_ResetPsOnly(); break; case PMF_SHUTDOWN_SUBTYPE_SYSTEM: + /* Bypass RPLL before SRST : Workaround for a bug in 1.0 Silicon */ + if (XPfw_PlatformGetPsVersion() == XPFW_PLATFORM_PS_V1) { + XPfw_UtilRMW(CRL_APB_RPLL_CTRL, CRL_APB_RPLL_CTRL_BYPASS_MASK, + CRL_APB_RPLL_CTRL_BYPASS_MASK); + } + XPfw_RMW32(CRL_APB_RESET_CTRL, CRL_APB_RESET_CTRL_SOFT_RESET_MASK, CRL_APB_RESET_CTRL_SOFT_RESET_MASK); -- 2.7.4