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All rightsreserved. ------------------------------------------------------------------- --library IEEE; --use IEEE.std_logic_1164.all; -- --entity axiaddrpref is -- generic ( -- C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000"; -- C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF"; -- C_S_AXI_ID_WIDTH: integer := 1; -- C_S_AXI_NATIVE_ID_WIDTH: integer := 8 -- previously 12 produced new errors -- ); -- port ( -- -- arid -- sg_s_axi_arid: in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); -- s_axi_arid: out std_logic_vector(C_S_AXI_NATIVE_ID_WIDTH-1 downto 0); -- -- awid -- sg_s_axi_awid: in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); -- s_axi_awid: out std_logic_vector(C_S_AXI_NATIVE_ID_WIDTH-1 downto 0); -- -- rid -- sg_s_axi_rid: out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); -- s_axi_rid: in std_logic_vector(C_S_AXI_NATIVE_ID_WIDTH-1 downto 0); -- -- bid -- sg_s_axi_bid: out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); -- s_axi_bid: in std_logic_vector(C_S_AXI_NATIVE_ID_WIDTH-1 downto 0) -- ); --end axiaddrpref; --architecture behavior of axiaddrpref is -- --begin -- --s_axi_arid(C_S_AXI_ID_WIDTH-1 downto 0) <= sg_s_axi_arid; --s_axi_awid(C_S_AXI_ID_WIDTH-1 downto 0) <= sg_s_axi_awid; -- --sg_s_axi_rid <= s_axi_rid(C_S_AXI_ID_WIDTH-1 downto 0); --sg_s_axi_bid <= s_axi_bid(C_S_AXI_ID_WIDTH-1 downto 0); -- --end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity testpcoremdl_axiw is generic ( C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000"; C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF"; C_S_AXI_ADDR_WIDTH: integer := 0; C_S_AXI_DATA_WIDTH: integer := 0; C_S_AXI_ID_WIDTH: integer := 0; C_S_AXI_SUPPORT_BURST: integer := 0 ); port ( axi_aclk: in std_logic; axi_aresetn: in std_logic; gateway_in: in std_logic_vector(0 to 15); gateway_in1: in std_logic_vector(0 to 15); s_axi_araddr: in std_logic_vector(0 to 31); s_axi_arburst: in std_logic_vector(0 to 1); s_axi_arcache: in std_logic_vector(0 to 3); s_axi_arid: in std_logic_vector(0 to C_S_AXI_ID_WIDTH-1); s_axi_arlen: in std_logic_vector(0 to 7); s_axi_arlock: in std_logic_vector(0 to 1); s_axi_arprot: in std_logic_vector(0 to 2); s_axi_arsize: in std_logic_vector(0 to 2); s_axi_arvalid: in std_logic; s_axi_awaddr: in std_logic_vector(0 to 31); s_axi_awburst: in std_logic_vector(0 to 1); s_axi_awcache: in std_logic_vector(0 to 3); s_axi_awid: in std_logic_vector(0 to C_S_AXI_ID_WIDTH-1); s_axi_awlen: in std_logic_vector(0 to 7); s_axi_awlock: in std_logic_vector(0 to 1); s_axi_awprot: in std_logic_vector(0 to 2); s_axi_awsize: in std_logic_vector(0 to 2); s_axi_awvalid: in std_logic; s_axi_bready: in std_logic; s_axi_rready: in std_logic; s_axi_wdata: in std_logic_vector(0 to 31); s_axi_wlast: in std_logic; s_axi_wstrb: in std_logic_vector(0 to 3); s_axi_wvalid: in std_logic; sysgen_clk: in std_logic; gateway_out: out std_logic_vector(0 to 16); s_axi_arready: out std_logic; s_axi_awready: out std_logic; s_axi_bid: out std_logic_vector(0 to C_S_AXI_ID_WIDTH-1); s_axi_bresp: out std_logic_vector(0 to 1); s_axi_bvalid: out std_logic; s_axi_rdata: out std_logic_vector(0 to 31); s_axi_rid: out std_logic_vector(0 to C_S_AXI_ID_WIDTH-1); s_axi_rlast: out std_logic; s_axi_rresp: out std_logic_vector(0 to 1); s_axi_rvalid: out std_logic; s_axi_wready: out std_logic ); end testpcoremdl_axiw; architecture structural of testpcoremdl_axiw is signal axi_aresetn_x0: std_logic; signal axiaddrpref_s_axi_arid_net: std_logic_vector(7 downto 0); signal axiaddrpref_s_axi_awid_net: std_logic_vector(7 downto 0); signal axiaddrpref_s_axi_bid_net: std_logic_vector(7 downto 0); signal axiaddrpref_s_axi_rid_net: std_logic_vector(7 downto 0); signal axiaddrpref_sg_s_axi_arid_net: std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); signal axiaddrpref_sg_s_axi_awid_net: std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); signal axiaddrpref_sg_s_axi_bid_net: std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); signal axiaddrpref_sg_s_axi_rid_net: std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); signal clk: std_logic; signal gateway_in1_x0: std_logic_vector(15 downto 0); signal gateway_in_x0: std_logic_vector(15 downto 0); signal gateway_out_x0: std_logic_vector(16 downto 0); signal s_axi_araddr_x0: std_logic_vector(31 downto 0); signal s_axi_arburst_x0: std_logic_vector(1 downto 0); signal s_axi_arcache_x0: std_logic_vector(3 downto 0); signal s_axi_arlen_x0: std_logic_vector(7 downto 0); signal s_axi_arlock_x0: std_logic_vector(1 downto 0); signal s_axi_arprot_x0: std_logic_vector(2 downto 0); signal s_axi_arready_x0: std_logic; signal s_axi_arsize_x0: std_logic_vector(2 downto 0); signal s_axi_arvalid_x0: std_logic; signal s_axi_awaddr_x0: std_logic_vector(31 downto 0); signal s_axi_awburst_x0: std_logic_vector(1 downto 0); signal s_axi_awcache_x0: std_logic_vector(3 downto 0); signal s_axi_awlen_x0: std_logic_vector(7 downto 0); signal s_axi_awlock_x0: std_logic_vector(1 downto 0); signal s_axi_awprot_x0: std_logic_vector(2 downto 0); signal s_axi_awready_x0: std_logic; signal s_axi_awsize_x0: std_logic_vector(2 downto 0); signal s_axi_awvalid_x0: std_logic; signal s_axi_bready_x0: std_logic; signal s_axi_bresp_x0: std_logic_vector(1 downto 0); signal s_axi_bvalid_x0: std_logic; signal s_axi_rdata_x0: std_logic_vector(31 downto 0); signal s_axi_rlast_x0: std_logic; signal s_axi_rready_x0: std_logic; signal s_axi_rresp_x0: std_logic_vector(1 downto 0); signal s_axi_rvalid_x0: std_logic; signal s_axi_wdata_x0: std_logic_vector(31 downto 0); signal s_axi_wlast_x0: std_logic; signal s_axi_wready_x0: std_logic; signal s_axi_wstrb_x0: std_logic_vector(3 downto 0); signal s_axi_wvalid_x0: std_logic; signal xps_clk: std_logic; begin xps_clk <= axi_aclk; axi_aresetn_x0 <= axi_aresetn; gateway_in_x0 <= gateway_in; gateway_in1_x0 <= gateway_in1; s_axi_araddr_x0 <= s_axi_araddr; s_axi_arburst_x0 <= s_axi_arburst; s_axi_arcache_x0 <= s_axi_arcache; axiaddrpref_sg_s_axi_arid_net <= s_axi_arid; s_axi_arlen_x0 <= s_axi_arlen; s_axi_arlock_x0 <= s_axi_arlock; s_axi_arprot_x0 <= s_axi_arprot; s_axi_arsize_x0 <= s_axi_arsize; s_axi_arvalid_x0 <= s_axi_arvalid; s_axi_awaddr_x0 <= s_axi_awaddr; s_axi_awburst_x0 <= s_axi_awburst; s_axi_awcache_x0 <= s_axi_awcache; axiaddrpref_sg_s_axi_awid_net <= s_axi_awid; s_axi_awlen_x0 <= s_axi_awlen; s_axi_awlock_x0 <= s_axi_awlock; s_axi_awprot_x0 <= s_axi_awprot; s_axi_awsize_x0 <= s_axi_awsize; s_axi_awvalid_x0 <= s_axi_awvalid; s_axi_bready_x0 <= s_axi_bready; s_axi_rready_x0 <= s_axi_rready; s_axi_wdata_x0 <= s_axi_wdata; s_axi_wlast_x0 <= s_axi_wlast; s_axi_wstrb_x0 <= s_axi_wstrb; s_axi_wvalid_x0 <= s_axi_wvalid; clk <= sysgen_clk; gateway_out <= gateway_out_x0; s_axi_arready <= s_axi_arready_x0; s_axi_awready <= s_axi_awready_x0; s_axi_bid <= axiaddrpref_sg_s_axi_bid_net; s_axi_bresp <= s_axi_bresp_x0; s_axi_bvalid <= s_axi_bvalid_x0; s_axi_rdata <= s_axi_rdata_x0; s_axi_rid <= axiaddrpref_sg_s_axi_rid_net; s_axi_rlast <= s_axi_rlast_x0; s_axi_rresp <= s_axi_rresp_x0; s_axi_rvalid <= s_axi_rvalid_x0; s_axi_wready <= s_axi_wready_x0; -- axiaddrpref_x0: entity work.axiaddrpref -- generic map ( -- C_BASEADDR => C_BASEADDR, -- C_HIGHADDR => C_HIGHADDR, -- C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH -- ) -- port map ( -- s_axi_arid => axiaddrpref_s_axi_arid_net, -- s_axi_awid => axiaddrpref_s_axi_awid_net, -- sg_s_axi_bid => axiaddrpref_sg_s_axi_bid_net, -- sg_s_axi_rid => axiaddrpref_sg_s_axi_rid_net, -- s_axi_bid => axiaddrpref_s_axi_bid_net, -- s_axi_rid => axiaddrpref_s_axi_rid_net, -- sg_s_axi_arid => axiaddrpref_sg_s_axi_arid_net, -- sg_s_axi_awid => axiaddrpref_sg_s_axi_awid_net -- ); sysgen_dut: entity work.testpcoremdl_cw port map ( axi_aresetn => axi_aresetn_x0, clk => clk, gateway_in => gateway_in_x0, gateway_in1 => gateway_in1_x0, s_axi_araddr => s_axi_araddr_x0, s_axi_arburst => s_axi_arburst_x0, s_axi_arcache => s_axi_arcache_x0, s_axi_arid => axiaddrpref_s_axi_arid_net, s_axi_arlen => s_axi_arlen_x0, s_axi_arlock => s_axi_arlock_x0, s_axi_arprot => s_axi_arprot_x0, s_axi_arsize => s_axi_arsize_x0, s_axi_arvalid => s_axi_arvalid_x0, s_axi_awaddr => s_axi_awaddr_x0, s_axi_awburst => s_axi_awburst_x0, s_axi_awcache => s_axi_awcache_x0, s_axi_awid => axiaddrpref_s_axi_awid_net, s_axi_awlen => s_axi_awlen_x0, s_axi_awlock => s_axi_awlock_x0, s_axi_awprot => s_axi_awprot_x0, s_axi_awsize => s_axi_awsize_x0, s_axi_awvalid => s_axi_awvalid_x0, s_axi_bready => s_axi_bready_x0, s_axi_rready => s_axi_rready_x0, s_axi_wdata => s_axi_wdata_x0, s_axi_wlast => s_axi_wlast_x0, s_axi_wstrb => s_axi_wstrb_x0, s_axi_wvalid => s_axi_wvalid_x0, xps_clk => xps_clk, gateway_out => gateway_out_x0, s_axi_arready => s_axi_arready_x0, s_axi_awready => s_axi_awready_x0, s_axi_bid => axiaddrpref_s_axi_bid_net, s_axi_bresp => s_axi_bresp_x0, s_axi_bvalid => s_axi_bvalid_x0, s_axi_rdata => s_axi_rdata_x0, s_axi_rid => axiaddrpref_s_axi_rid_net, s_axi_rlast => s_axi_rlast_x0, s_axi_rresp => s_axi_rresp_x0, s_axi_rvalid => s_axi_rvalid_x0, s_axi_wready => s_axi_wready_x0 ); end structural;